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46 lines
2.1 KiB
46 lines
2.1 KiB
20 years ago
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README on the IOBARRIER for CardEngine IO
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=========================================
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Due to an unfortunate oversight when the Card Engines were designed,
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the signals that control access to some peripherals, most notably the
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SMC91C9111 ethernet controller, are not properly handled.
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The symptom is that some back to back IO with the peripheral returns
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unreliable data. With the SMC chip, you'll see errors about the bank
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register being 'screwed'.
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The cause is that the AEN signal to the SMC chip does not transition
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for every memory access. It is driven through the CPLD from the CS7
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line of the CPU's static memory controller which is optimized to
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eliminate unnecessary transitions. Yet, the SMC requires a transition
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for every write access. The Sharp website has more information about
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the effect this power-conserving feature has on peripheral
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interfacing.
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The solution is to follow every write access to the SMC chip with an
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access to another memory region that will force the CPU to release the
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chip select line. It is important to guarantee that this access
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forces the CPU off-chip. We map a page of SDRAM as if it were an
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uncacheable IO device and read from it after every SMC IO write
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operation.
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SMC IO
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BARRIER IO
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Only this sequence is important. It does not matter that there is no
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BARRIER IO before the access to the SMC chip because the AEN latch
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only needs occurs after the SMC IO write cycle. The routines that
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implement this work-around make an additional concession which is to
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disable interrupts during the IO sequence. Other hardware devices
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(the LogicPD CPLD) have registers in the same the physical memory
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region as the SMC chip. An interrupt might allow an access to one of
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those registers while SMC IO is being performed.
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You might be tempted to think that we have to access another device
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attached to the static memory controller, but the empirical evidence
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indicates that this is not so. Mapping 0x00000000 (flash) and
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0xc0000000 (SDRAM) appear to have the same effect. Using SDRAM seems
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to be faster. Choosing to access an undecoded memory region is not
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desirable as there is no way to know how that chip select will be used
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in the future.
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