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/* rwsem.S: RW semaphore assembler.
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*
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* Written by David S. Miller (davem@redhat.com), 2001.
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* Derived from asm-i386/rwsem.h
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*/
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#include <asm/rwsem-const.h>
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.section .sched.text, "ax"
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.globl __down_read
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__down_read:
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1: lduw [%o0], %g1
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add %g1, 1, %g7
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cas [%o0], %g1, %g7
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cmp %g1, %g7
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bne,pn %icc, 1b
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add %g7, 1, %g7
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cmp %g7, 0
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
20 years ago
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membar #StoreLoad | #StoreStore
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bl,pn %icc, 3f
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
20 years ago
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nop
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2:
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retl
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nop
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3:
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save %sp, -192, %sp
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call rwsem_down_read_failed
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mov %i0, %o0
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ret
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restore
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.size __down_read, .-__down_read
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.globl __down_read_trylock
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__down_read_trylock:
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1: lduw [%o0], %g1
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add %g1, 1, %g7
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cmp %g7, 0
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bl,pn %icc, 2f
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mov 0, %o1
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cas [%o0], %g1, %g7
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cmp %g1, %g7
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bne,pn %icc, 1b
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mov 1, %o1
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membar #StoreLoad | #StoreStore
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2: retl
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mov %o1, %o0
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.size __down_read_trylock, .-__down_read_trylock
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.globl __down_write
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__down_write:
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sethi %hi(RWSEM_ACTIVE_WRITE_BIAS), %g1
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or %g1, %lo(RWSEM_ACTIVE_WRITE_BIAS), %g1
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1:
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lduw [%o0], %g3
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add %g3, %g1, %g7
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cas [%o0], %g3, %g7
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cmp %g3, %g7
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bne,pn %icc, 1b
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cmp %g7, 0
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
20 years ago
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membar #StoreLoad | #StoreStore
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bne,pn %icc, 3f
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
20 years ago
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nop
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2: retl
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nop
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3:
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save %sp, -192, %sp
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call rwsem_down_write_failed
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mov %i0, %o0
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ret
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restore
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.size __down_write, .-__down_write
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.globl __down_write_trylock
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__down_write_trylock:
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sethi %hi(RWSEM_ACTIVE_WRITE_BIAS), %g1
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or %g1, %lo(RWSEM_ACTIVE_WRITE_BIAS), %g1
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1:
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lduw [%o0], %g3
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cmp %g3, 0
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bne,pn %icc, 2f
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mov 0, %o1
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add %g3, %g1, %g7
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cas [%o0], %g3, %g7
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cmp %g3, %g7
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bne,pn %icc, 1b
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mov 1, %o1
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membar #StoreLoad | #StoreStore
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2: retl
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mov %o1, %o0
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.size __down_write_trylock, .-__down_write_trylock
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.globl __up_read
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__up_read:
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1:
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lduw [%o0], %g1
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sub %g1, 1, %g7
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cas [%o0], %g1, %g7
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cmp %g1, %g7
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bne,pn %icc, 1b
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cmp %g7, 0
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
20 years ago
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membar #StoreLoad | #StoreStore
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bl,pn %icc, 3f
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
20 years ago
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nop
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2: retl
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nop
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3: sethi %hi(RWSEM_ACTIVE_MASK), %g1
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sub %g7, 1, %g7
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or %g1, %lo(RWSEM_ACTIVE_MASK), %g1
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andcc %g7, %g1, %g0
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bne,pn %icc, 2b
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nop
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save %sp, -192, %sp
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call rwsem_wake
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mov %i0, %o0
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ret
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restore
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.size __up_read, .-__up_read
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.globl __up_write
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__up_write:
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sethi %hi(RWSEM_ACTIVE_WRITE_BIAS), %g1
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or %g1, %lo(RWSEM_ACTIVE_WRITE_BIAS), %g1
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1:
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lduw [%o0], %g3
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sub %g3, %g1, %g7
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cas [%o0], %g3, %g7
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cmp %g3, %g7
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bne,pn %icc, 1b
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sub %g7, %g1, %g7
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cmp %g7, 0
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
20 years ago
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membar #StoreLoad | #StoreStore
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bl,pn %icc, 3f
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
20 years ago
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nop
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2:
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retl
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nop
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3:
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save %sp, -192, %sp
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call rwsem_wake
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mov %i0, %o0
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ret
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restore
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.size __up_write, .-__up_write
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.globl __downgrade_write
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__downgrade_write:
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sethi %hi(RWSEM_WAITING_BIAS), %g1
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or %g1, %lo(RWSEM_WAITING_BIAS), %g1
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1:
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lduw [%o0], %g3
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sub %g3, %g1, %g7
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cas [%o0], %g3, %g7
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cmp %g3, %g7
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bne,pn %icc, 1b
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sub %g7, %g1, %g7
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cmp %g7, 0
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
20 years ago
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membar #StoreLoad | #StoreStore
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bl,pn %icc, 3f
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
20 years ago
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nop
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2:
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retl
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nop
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3:
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save %sp, -192, %sp
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call rwsem_downgrade_wake
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mov %i0, %o0
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ret
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restore
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.size __downgrade_write, .-__downgrade_write
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