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203 lines
6.5 KiB
203 lines
6.5 KiB
20 years ago
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/*
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* include/asm-v850/rte_me2_cb.h -- Midas labs RTE-V850E/ME2-CB board
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*
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* Copyright (C) 2001,02,03 NEC Corporation
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* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#ifndef __V850_RTE_ME2_CB_H__
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#define __V850_RTE_ME2_CB_H__
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#include <asm/rte_cb.h> /* Common defs for Midas RTE-CB boards. */
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#define PLATFORM "rte-v850e/me2-cb"
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#define PLATFORM_LONG "Midas lab RTE-V850E/ME2-CB"
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#define CPU_CLOCK_FREQ 150000000 /* 150MHz */
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#define FIXED_BOGOMIPS 50
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/* 32MB of onbard SDRAM. */
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#define SDRAM_ADDR 0x00800000
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#define SDRAM_SIZE 0x02000000 /* 32MB */
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/* CPU addresses of GBUS memory spaces. */
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#define GCS0_ADDR 0x04000000 /* GCS0 - Common SRAM (2MB) */
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#define GCS0_SIZE 0x00800000 /* 8MB */
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#define GCS1_ADDR 0x04800000 /* GCS1 - Flash ROM (8MB) */
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#define GCS1_SIZE 0x00800000 /* 8MB */
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#define GCS2_ADDR 0x07000000 /* GCS2 - I/O registers */
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#define GCS2_SIZE 0x00800000 /* 8MB */
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#define GCS5_ADDR 0x08000000 /* GCS5 - PCI bus space */
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#define GCS5_SIZE 0x02000000 /* 32MB */
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#define GCS6_ADDR 0x07800000 /* GCS6 - PCI control registers */
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#define GCS6_SIZE 0x00800000 /* 8MB */
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/* For <asm/page.h> */
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#define PAGE_OFFSET SDRAM_ADDR
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#ifdef CONFIG_ROM_KERNEL
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/* Kernel is in ROM, starting at address 0. */
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#define INTV_BASE 0
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#define ROOT_FS_IMAGE_RW 0
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#else /* !CONFIG_ROM_KERNEL */
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/* Using RAM-kernel. Assume some sort of boot-loader got us loaded at
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address 0. */
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#define INTV_BASE 0
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#define ROOT_FS_IMAGE_RW 1
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#endif /* CONFIG_ROM_KERNEL */
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/* Some misc. on-board devices. */
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/* Seven-segment LED display (four digits). */
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#define LED_ADDR(n) (0x0FE02000 + (n))
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#define LED(n) (*(volatile unsigned char *)LED_ADDR(n))
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#define LED_NUM_DIGITS 4
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/* On-board PIC. */
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#define CB_PIC_BASE_ADDR 0x0FE04000
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#define CB_PIC_INT0M_ADDR (CB_PIC_BASE_ADDR + 0x00)
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#define CB_PIC_INT0M (*(volatile u16 *)CB_PIC_INT0M_ADDR)
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#define CB_PIC_INT1M_ADDR (CB_PIC_BASE_ADDR + 0x10)
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#define CB_PIC_INT1M (*(volatile u16 *)CB_PIC_INT1M_ADDR)
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#define CB_PIC_INTR_ADDR (CB_PIC_BASE_ADDR + 0x20)
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#define CB_PIC_INTR (*(volatile u16 *)CB_PIC_INTR_ADDR)
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#define CB_PIC_INTEN_ADDR (CB_PIC_BASE_ADDR + 0x30)
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#define CB_PIC_INTEN (*(volatile u16 *)CB_PIC_INTEN_ADDR)
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#define CB_PIC_INT0EN 0x0001
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#define CB_PIC_INT1EN 0x0002
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#define CB_PIC_INT0SEL 0x0080
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/* The PIC interrupts themselves. */
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#define CB_PIC_BASE_IRQ NUM_CPU_IRQS
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#define IRQ_CB_PIC_NUM 10
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/* Some specific CB_PIC interrupts. */
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#define IRQ_CB_EXTTM0 (CB_PIC_BASE_IRQ + 0)
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#define IRQ_CB_EXTSIO (CB_PIC_BASE_IRQ + 1)
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#define IRQ_CB_TOVER (CB_PIC_BASE_IRQ + 2)
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#define IRQ_CB_GINT0 (CB_PIC_BASE_IRQ + 3)
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#define IRQ_CB_USB (CB_PIC_BASE_IRQ + 4)
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#define IRQ_CB_LANC (CB_PIC_BASE_IRQ + 5)
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#define IRQ_CB_USB_VBUS_ON (CB_PIC_BASE_IRQ + 6)
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#define IRQ_CB_USB_VBUS_OFF (CB_PIC_BASE_IRQ + 7)
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#define IRQ_CB_EXTTM1 (CB_PIC_BASE_IRQ + 8)
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#define IRQ_CB_EXTTM2 (CB_PIC_BASE_IRQ + 9)
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/* The GBUS GINT1 - GINT3 (note, not GINT0!) interrupts are connected to
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the INTP65 - INTP67 pins on the CPU. These are shared among the GBUS
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interrupts. */
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#define IRQ_GINT(n) IRQ_INTP((n) + 9) /* 0 is unused! */
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#define IRQ_GINT_NUM 4 /* 0 is unused! */
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/* The shared interrupt line from the PIC is connected to CPU pin INTP23. */
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#define IRQ_CB_PIC IRQ_INTP(4) /* P23 */
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/* Used by <asm/rte_cb.h> to derive NUM_MACH_IRQS. */
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#define NUM_RTE_CB_IRQS (NUM_CPU_IRQS + IRQ_CB_PIC_NUM)
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#ifndef __ASSEMBLY__
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struct cb_pic_irq_init {
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const char *name; /* name of interrupt type */
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/* Range of kernel irq numbers for this type:
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BASE, BASE+INTERVAL, ..., BASE+INTERVAL*NUM */
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unsigned base, num, interval;
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unsigned priority; /* interrupt priority to assign */
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};
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struct hw_interrupt_type; /* fwd decl */
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/* Enable interrupt handling for interrupt IRQ. */
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extern void cb_pic_enable_irq (unsigned irq);
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/* Disable interrupt handling for interrupt IRQ. Note that any interrupts
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received while disabled will be delivered once the interrupt is enabled
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again, unless they are explicitly cleared using `cb_pic_clear_pending_irq'. */
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extern void cb_pic_disable_irq (unsigned irq);
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/* Initialize HW_IRQ_TYPES for PIC irqs described in array INITS (which is
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terminated by an entry with the name field == 0). */
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extern void cb_pic_init_irq_types (struct cb_pic_irq_init *inits,
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struct hw_interrupt_type *hw_irq_types);
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/* Initialize PIC interrupts. */
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extern void cb_pic_init_irqs (void);
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#endif /* __ASSEMBLY__ */
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/* TL16C550C on board UART see also asm/serial.h */
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#define CB_UART_BASE 0x0FE08000
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#define CB_UART_REG_GAP 0x10
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#define CB_UART_CLOCK 0x16000000
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/* CompactFlash setting */
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#define CB_CF_BASE 0x0FE0C000
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#define CB_CF_CCR_ADDR (CB_CF_BASE+0x200)
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#define CB_CF_CCR (*(volatile u8 *)CB_CF_CCR_ADDR)
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#define CB_CF_REG0_ADDR (CB_CF_BASE+0x1000)
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#define CB_CF_REG0 (*(volatile u16 *)CB_CF_REG0_ADDR)
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#define CB_CF_STS0_ADDR (CB_CF_BASE+0x1004)
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#define CB_CF_STS0 (*(volatile u16 *)CB_CF_STS0_ADDR)
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#define CB_PCATA_BASE (CB_CF_BASE+0x800)
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#define CB_IDE_BASE (CB_CF_BASE+0x9F0)
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#define CB_IDE_CTRL (CB_CF_BASE+0xBF6)
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#define CB_IDE_REG_OFFS 0x1
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/* SMSC LAN91C111 setting */
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#if defined(CONFIG_SMC91111)
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#define CB_LANC_BASE 0x0FE10300
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#define CONFIG_SMC16BITONLY
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#define ETH0_ADDR CB_LANC_BASE
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#define ETH0_IRQ IRQ_CB_LANC
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#endif /* CONFIG_SMC16BITONLY */
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#undef V850E_UART_PRE_CONFIGURE
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#define V850E_UART_PRE_CONFIGURE rte_me2_cb_uart_pre_configure
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#ifndef __ASSEMBLY__
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extern void rte_me2_cb_uart_pre_configure (unsigned chan,
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unsigned cflags, unsigned baud);
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#endif /* __ASSEMBLY__ */
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/* This board supports RTS/CTS for the on-chip UART, but only for channel 0. */
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/* CTS for UART channel 0 is pin P22 (bit 2 of port 2). */
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#define V850E_UART_CTS(chan) ((chan) == 0 ? !(ME2_PORT2_IO & 0x4) : 1)
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/* RTS for UART channel 0 is pin P21 (bit 1 of port 2). */
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#define V850E_UART_SET_RTS(chan, val) \
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do { \
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if (chan == 0) { \
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unsigned old = ME2_PORT2_IO; \
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if (val) \
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ME2_PORT2_IO = old & ~0x2; \
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else \
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ME2_PORT2_IO = old | 0x2; \
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} \
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} while (0)
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#ifndef __ASSEMBLY__
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extern void rte_me2_cb_init_irqs (void);
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#endif /* !__ASSEMBLY__ */
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#endif /* __V850_RTE_ME2_CB_H__ */
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