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#
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# Coresight configuration
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#
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menuconfig CORESIGHT
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bool "CoreSight Tracing Support"
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select ARM_AMBA
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select PERF_EVENTS
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help
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This framework provides a kernel interface for the CoreSight debug
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and trace drivers to register themselves with. It's intended to build
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a topological view of the CoreSight components based on a DT
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specification and configure the right series of components when a
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trace source gets enabled.
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if CORESIGHT
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config CORESIGHT_LINKS_AND_SINKS
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bool "CoreSight Link and Sink drivers"
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help
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This enables support for CoreSight link and sink drivers that are
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responsible for transporting and collecting the trace data
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respectively. Link and sinks are dynamically aggregated with a trace
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entity at run time to form a complete trace path.
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config CORESIGHT_LINK_AND_SINK_TMC
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bool "Coresight generic TMC driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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select CORESIGHT_CSR
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help
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This enables support for the Trace Memory Controller driver.
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Depending on its configuration the device can act as a link (embedded
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trace router - ETR) or sink (embedded trace FIFO). The driver
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complies with the generic implementation of the component without
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special enhancement or added features.
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config CORESIGHT_CATU
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bool "Coresight Address Translation Unit (CATU) driver"
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depends on CORESIGHT_LINK_AND_SINK_TMC
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help
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Enable support for the Coresight Address Translation Unit (CATU).
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CATU supports a scatter gather table of 4K pages, with forward/backward
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lookup. CATU helps TMC ETR to use a large physically non-contiguous trace
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buffer by translating the addresses used by ETR to the physical address
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by looking up the provided table. CATU can also be used in pass-through
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mode where the address is not translated.
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config CORESIGHT_SINK_TPIU
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bool "Coresight generic TPIU driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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help
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This enables support for the Trace Port Interface Unit driver,
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responsible for bridging the gap between the on-chip coresight
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components and a trace for bridging the gap between the on-chip
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coresight components and a trace port collection engine, typically
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connected to an external host for use case capturing more traces than
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the on-board coresight memory can handle.
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config CORESIGHT_SINK_ETBV10
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bool "Coresight ETBv1.0 driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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help
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This enables support for the Embedded Trace Buffer version 1.0 driver
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that complies with the generic implementation of the component without
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special enhancement or added features.
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config CORESIGHT_SOURCE_ETM3X
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bool "CoreSight Embedded Trace Macrocell 3.x driver"
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depends on !ARM64
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select CORESIGHT_LINKS_AND_SINKS
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help
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This driver provides support for processor ETM3.x and PTM1.x modules,
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which allows tracing the instructions that a processor is executing
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This is primarily useful for instruction level tracing. Depending
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the ETM version data tracing may also be available.
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config CORESIGHT_SOURCE_ETM4X
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bool "CoreSight Embedded Trace Macrocell 4.x driver"
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select CORESIGHT_LINKS_AND_SINKS
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select PID_IN_CONTEXTIDR
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help
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This driver provides support for the ETM4.x tracer module, tracing the
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instructions that a processor is executing. This is primarily useful
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for instruction level tracing. Depending on the implemented version
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data tracing may also be available.
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config CORESIGHT_DYNAMIC_REPLICATOR
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bool "CoreSight Programmable Replicator driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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help
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This enables support for dynamic CoreSight replicator link driver.
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The programmable ATB replicator allows independent filtering of the
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trace data based on the traceid.
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config CORESIGHT_DBGUI
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bool "CoreSight DebugUI driver"
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help
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This driver provides support for DebugUI that helps to capture
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the value at a specified address. It allows configuring DebugUI
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to select specified address and trigger mode based on user
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input.
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config CORESIGHT_STM
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bool "CoreSight System Trace Macrocell driver"
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depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64
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select CORESIGHT_LINKS_AND_SINKS
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select STM
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select CORESIGHT_OST
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help
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This driver provides support for hardware assisted software
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instrumentation based tracing. This is primarily used for
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logging useful software events or data coming from various entities
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in the system, possibly running different OSs
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coresight: add support for CPU debug module
Coresight includes debug module and usually the module connects with CPU
debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
description for related info in "Part H: External Debug".
Chapter H7 "The Sample-based Profiling Extension" introduces several
sampling registers, e.g. we can check program counter value with
combined CPU exception level, secure state, etc. So this is helpful for
analysis CPU lockup scenarios, e.g. if one CPU has run into infinite
loop with IRQ disabled. In this case the CPU cannot switch context and
handle any interrupt (including IPIs), as the result it cannot handle
SMP call for stack dump.
This patch is to enable coresight debug module, so firstly this driver
is to bind apb clock for debug module and this is to ensure the debug
module can be accessed from program or external debugger. And the driver
uses sample-based registers for debug purpose, e.g. when system triggers
panic, the driver will dump program counter and combined context
registers (EDCIDSR, EDVIDSR); by parsing context registers so can
quickly get to know CPU secure state, exception level, etc.
Some of the debug module registers are located in CPU power domain, so
this requires the CPU power domain stays on when access related debug
registers, but the power management for CPU power domain is quite
dependent on SoC integration for power management. For the platforms
which with sane power controller implementations, this driver follows
the method to set EDPRCR to try to pull the CPU out of low power state
and then set 'no power down request' bit so the CPU has no chance to
lose power.
If the SoC has not followed up this design well for power management
controller, the user should use the command line parameter or sysfs
to constrain all or partial idle states to ensure the CPU power
domain is enabled and access coresight CPU debug component safely.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
8 years ago
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config CORESIGHT_CPU_DEBUG
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tristate "CoreSight CPU Debug driver"
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depends on ARM || ARM64
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depends on DEBUG_FS
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help
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This driver provides support for coresight debugging module. This
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is primarily used to dump sample-based profiling registers when
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system triggers panic, the driver will parse context registers so
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can quickly get to know program counter (PC), secure state,
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exception level, etc. Before use debugging functionality, platform
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needs to ensure the clock domain and power domain are enabled
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properly, please refer Documentation/trace/coresight-cpu-debug.txt
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for detailed description and the example for usage.
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config CORESIGHT_CTI
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bool "CoreSight Cross Trigger Interface driver"
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help
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This driver provides support for Cross Trigger Interface that is
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used to input or output i.e. pass cross trigger events from one
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hardware component to another. It can also be used to pass
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software generated events.
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config CORESIGHT_OST
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bool "CoreSight OST framework"
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depends on CORESIGHT_STM
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help
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This driver enables the support for Open System Trace packets in STM.
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This is primarily intended to be used as a layer on top of underlying
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physical byte transport mechanisms.
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config CORESIGHT_TPDA
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bool "CoreSight Trace, Profiling & Diagnostics Aggregator driver"
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help
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This driver provides support for configuring aggregator. This is
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primarily useful for pulling the data sets from one or more
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attached monitors and pushing the resultant data out. Multiple
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monitors are connected on different input ports of TPDA.
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config CORESIGHT_TPDM
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bool "CoreSight Trace, Profiling & Diagnostics Monitor driver"
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help
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This driver provides support for configuring monitor. Monitors are
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primarily responsible for data set collection and support the
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ability to collect any permutation of data set types. Monitors are
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also responsible for interaction with system cross triggering.
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config CORESIGHT_TPDM_DEFAULT_ENABLE
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bool "Turn on TPDM tracing by default"
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depends on CORESIGHT_TPDM
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help
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Turns on CoreSight TPDM tracing for different data set types by
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default. Otherwise, tracing is disabled by default but can be
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enabled via sysfs.
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If unsure, say 'N' here to avoid potential power and performance
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penalty.
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config CORESIGHT_QPDI
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bool "CoreSight PMIC debug interface support"
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help
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This driver provides support for controlling the PMIC debug interface
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feature. When enabled via sysfs it allows disagnostic access to the
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PMIC. Similarly this debug feature can be disabled via sysfs which
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prevents debug dongle detection.
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config CORESIGHT_HWEVENT
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bool "CoreSight Hardware Event driver"
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depends on CORESIGHT_STM
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select CORESIGHT_CSR
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help
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This driver provides support for monitoring and tracing CoreSight
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Hardware Event across STM interface. It configures Coresight
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Hardware Event mux control registers to select hardware events
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based on user input.
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config CORESIGHT_DUMMY
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bool "Dummy driver support"
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help
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Enables support for dummy driver. Dummy driver can be
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used for CoreSight sources/sinks that are owned and configured by some other
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subsystem and use Linux drivers to configure rest of trace path.
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config CORESIGHT_REMOTE_ETM
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bool "Remote processor ETM trace support"
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depends on QCOM_QMI_HELPERS
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help
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Enables support for ETM trace collection on remote processor using
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CoreSight framework. Enabling this will allow turning on ETM
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tracing on remote processor via sysfs by configuring the required
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CoreSight components.
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config CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE
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int "default enable ETM for Remote processor based on instance id"
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depends on CORESIGHT_REMOTE_ETM
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help
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Support for enabling separated Remote processor ETM tracing. Depends
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on if instance id bit is set.
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config CORESIGHT_CSR
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bool "CoreSight Slave Register driver"
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help
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This driver provides support for CoreSight Slave Register block
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that hosts miscellaneous configuration registers.
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Those configuration registers can be used to control, various
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coresight configurations.
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config CORESIGHT_TGU
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bool "CoreSight Trigger Generation Unit driver"
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help
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This driver provides support for Trigger Generation Unit that is
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used to detect patterns or sequences on a given set of signals.
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TGU is used to monitor a particular bus within a given region to
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detect illegal transaction sequences or slave responses. It is also
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used to monitor a data stream to detect protocol violations and to
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provide a trigger point for centering data around a specific event
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within the trace data buffer.
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config CORESIGHT_EVENT
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tristate "CoreSight Event driver"
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help
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This driver provides support for registering with various events
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and performing CoreSight actions like aborting trace on their
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occurrence. These events can be controlled by using module
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parameters.
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endif
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