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109 lines
3.5 KiB
109 lines
3.5 KiB
20 years ago
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/*
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*
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* BRIEF MODULE DESCRIPTION
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* IT8172 system controller specific pci defines.
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*
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* Copyright 2000 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _8172PCI_H_
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#define _8172PCI_H_
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// PCI configuration space Type0
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#define PCI_IDREG 0x00
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#define PCI_CMDSTSREG 0x04
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#define PCI_CLASSREG 0x08
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#define PCI_BHLCREG 0x0C
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#define PCI_BASE1REG 0x10
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#define PCI_BASE2REG 0x14
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#define PCI_BASE3REG 0x18
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#define PCI_BASE4REG 0x1C
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#define PCI_BASE5REG 0x20
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#define PCI_BASE6REG 0x24
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#define PCI_ROMBASEREG 0x30
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#define PCI_INTRREG 0x3C
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// PCI configuration space Type1
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#define PCI_BUSNOREG 0x18
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#define IT_PCI_VENDORID(x) ((x) & 0xFFFF)
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#define IT_PCI_DEVICEID(x) (((x)>>16) & 0xFFFF)
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// Command register
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#define PCI_CMD_IOEN 0x00000001
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#define PCI_CMD_MEMEN 0x00000002
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#define PCI_CMD_BUSMASTER 0x00000004
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#define PCI_CMD_SPCYCLE 0x00000008
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#define PCI_CMD_WRINV 0x00000010
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#define PCI_CMD_VGASNOOP 0x00000020
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#define PCI_CMD_PERR 0x00000040
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#define PCI_CMD_WAITCTRL 0x00000080
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#define PCI_CMD_SERR 0x00000100
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#define PCI_CMD_FAST_BACKTOBACK 0x00000200
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// Status register
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#define PCI_STS_66MHZ 0x00200000
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#define PCI_STS_SUPPORT_UDF 0x00400000
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#define PCI_STS_FAST_BACKTOBACK 0x00800000
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#define PCI_STS_DATA_PERR 0x01000000
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#define PCI_STS_DEVSEL0 0x02000000
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#define PCI_STS_DEVSEL1 0x04000000
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#define PCI_STS_SIG_TGTABORT 0x08000000
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#define PCI_STS_RCV_TGTABORT 0x10000000
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#define PCI_STS_RCV_MSTABORT 0x20000000
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#define PCI_STS_SYSERR 0x40000000
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#define PCI_STS_DETCT_PERR 0x80000000
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#define IT_PCI_CLASS(x) (((x)>>24) & 0xFF)
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#define IT_PCI_SUBCLASS(x) (((x)>>16) & 0xFF)
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#define IT_PCI_INTERFACE(x) (((x)>>8) & 0xFF)
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#define IT_PCI_REVISION(x) ((x) & 0xFF)
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// PCI class code
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#define PCI_CLASS_BRIDGE 0x06
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// bridge subclass
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#define PCI_SUBCLASS_BRIDGE_HOST 0x00
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#define PCI_SUBCLASS_BRIDGE_PCI 0x04
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// BHLCREG
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#define IT_PCI_BIST(x) (((x)>>24) & 0xFF)
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#define IT_PCI_HEADERTYPE(x) (((x)>>16) & 0xFF)
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#define IT_PCI_LATENCYTIMER(x) (((x)>>8) & 0xFF)
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#define IT_PCI_CACHELINESIZE(x) ((x) & 0xFF)
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#define PCI_MULTIFUNC 0x80
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// INTRREG
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#define IT_PCI_MAXLAT(x) (((x)>>24) & 0xFF)
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#define IT_PCI_MINGNT(x) (((x)>>16) & 0xFF)
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#define IT_PCI_INTRPIN(x) (((x)>>8) & 0xFF)
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#define IT_PCI_INTRLINE(x) ((x) & 0xFF)
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#define PCI_VENDOR_NEC 0x1033
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#define PCI_VENDOR_DEC 0x1101
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#endif // _8172PCI_H_
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