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123 lines
4.0 KiB
123 lines
4.0 KiB
20 years ago
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/*
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* arch/ppc/platforms/mcpn765.h
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*
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* Definitions for Motorola MCG MCPN765 cPCI Board.
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*
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* Author: Mark A. Greer
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* mgreer@mvista.com
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*
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* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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/*
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* From Processor to PCI:
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* PCI Mem Space: 0x80000000 - 0xc0000000 -> 0x80000000 - 0xc0000000 (1 GB)
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* PCI I/O Space: 0xfd800000 - 0xfe000000 -> 0x00000000 - 0x00800000 (8 MB)
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* Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
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* MPIC in PCI Mem Space: 0xfe800000 - 0xfe830000 (not all used by MPIC)
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*
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* From PCI to Processor:
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* System Memory: 0x00000000 -> 0x00000000
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*/
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#ifndef __PPC_PLATFORMS_MCPN765_H
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#define __PPC_PLATFORMS_MCPN765_H
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#include <linux/config.h>
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/* PCI Memory space mapping info */
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#define MCPN765_PCI_MEM_SIZE 0x40000000U
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#define MCPN765_PROC_PCI_MEM_START 0x80000000U
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#define MCPN765_PROC_PCI_MEM_END (MCPN765_PROC_PCI_MEM_START + \
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MCPN765_PCI_MEM_SIZE - 1)
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#define MCPN765_PCI_MEM_START 0x80000000U
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#define MCPN765_PCI_MEM_END (MCPN765_PCI_MEM_START + \
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MCPN765_PCI_MEM_SIZE - 1)
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/* PCI I/O space mapping info */
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#define MCPN765_PCI_IO_SIZE 0x00800000U
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#define MCPN765_PROC_PCI_IO_START 0xfd800000U
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#define MCPN765_PROC_PCI_IO_END (MCPN765_PROC_PCI_IO_START + \
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MCPN765_PCI_IO_SIZE - 1)
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#define MCPN765_PCI_IO_START 0x00000000U
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#define MCPN765_PCI_IO_END (MCPN765_PCI_IO_START + \
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MCPN765_PCI_IO_SIZE - 1)
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/* System memory mapping info */
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#define MCPN765_PCI_DRAM_OFFSET 0x00000000U
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#define MCPN765_PCI_PHY_MEM_OFFSET 0x00000000U
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#define MCPN765_ISA_MEM_BASE 0x00000000U
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#define MCPN765_ISA_IO_BASE MCPN765_PROC_PCI_IO_START
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/* Define base addresses for important sets of registers */
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#define MCPN765_HAWK_MPIC_BASE 0xfe800000U
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#define MCPN765_HAWK_SMC_BASE 0xfef80000U
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#define MCPN765_HAWK_PPC_REG_BASE 0xfeff0000U
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/* Define MCPN765 board register addresses. */
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#define MCPN765_BOARD_STATUS_REG 0xfef88080U
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#define MCPN765_BOARD_MODFAIL_REG 0xfef88090U
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#define MCPN765_BOARD_MODRST_REG 0xfef880a0U
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#define MCPN765_BOARD_TBEN_REG 0xfef880c0U
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#define MCPN765_BOARD_GEOGRAPHICAL_REG 0xfef880e8U
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#define MCPN765_BOARD_EXT_FEATURE_REG 0xfef880f0U
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#define MCPN765_BOARD_LAST_RESET_REG 0xfef880f8U
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/* Defines for UART */
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/* Define the UART base addresses */
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#define MCPN765_SERIAL_1 0xfef88000
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#define MCPN765_SERIAL_2 0xfef88200
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#define MCPN765_SERIAL_3 0xfef88400
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#define MCPN765_SERIAL_4 0xfef88600
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#ifdef CONFIG_SERIAL_MANY_PORTS
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#define RS_TABLE_SIZE 64
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#else
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#define RS_TABLE_SIZE 4
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#endif
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/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
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#define BASE_BAUD ( 1843200 / 16 )
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#define UART_CLK 1843200
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#ifdef CONFIG_SERIAL_DETECT_IRQ
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#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
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#else
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#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
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#endif
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/* All UART IRQ's are wire-OR'd to IRQ 17 */
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#define STD_SERIAL_PORT_DFNS \
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{ 0, BASE_BAUD, MCPN765_SERIAL_1, 17, STD_COM_FLAGS, /* ttyS0 */\
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iomem_base: (u8 *)MCPN765_SERIAL_1, \
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iomem_reg_shift: 4, \
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io_type: SERIAL_IO_MEM }, \
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{ 0, BASE_BAUD, MCPN765_SERIAL_2, 17, STD_COM_FLAGS, /* ttyS1 */\
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iomem_base: (u8 *)MCPN765_SERIAL_2, \
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iomem_reg_shift: 4, \
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io_type: SERIAL_IO_MEM }, \
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{ 0, BASE_BAUD, MCPN765_SERIAL_3, 17, STD_COM_FLAGS, /* ttyS2 */\
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iomem_base: (u8 *)MCPN765_SERIAL_3, \
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iomem_reg_shift: 4, \
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io_type: SERIAL_IO_MEM }, \
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{ 0, BASE_BAUD, MCPN765_SERIAL_4, 17, STD_COM_FLAGS, /* ttyS3 */\
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iomem_base: (u8 *)MCPN765_SERIAL_4, \
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iomem_reg_shift: 4, \
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io_type: SERIAL_IO_MEM },
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#define SERIAL_PORT_DFNS \
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STD_SERIAL_PORT_DFNS
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/* Define the NVRAM/RTC address strobe & data registers */
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#define MCPN765_PHYS_NVRAM_AS0 0xfef880c8U
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#define MCPN765_PHYS_NVRAM_AS1 0xfef880d0U
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#define MCPN765_PHYS_NVRAM_DATA 0xfef880d8U
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extern void mcpn765_find_bridges(void);
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#endif /* __PPC_PLATFORMS_MCPN765_H */
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