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59 lines
1.7 KiB
59 lines
1.7 KiB
20 years ago
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/* linux/include/asm-arm/arch-s3c2410/bast-cpld.h
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*
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* (c) 2003,2004 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* BAST - CPLD control constants
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Changelog:
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* 25-May-2003 BJD Created file, added CTRL1 registers
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* 30-Aug-2004 BJD Updated definitions from 2.4.26 port
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* 30-Aug-2004 BJD Added CTRL3 and CTRL4 definitions
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*/
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#ifndef __ASM_ARCH_BASTCPLD_H
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#define __ASM_ARCH_BASTCPLD_H
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/* CTRL1 - Audio LR routing */
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#define BAST_CPLD_CTRL1_LRCOFF (0x00)
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#define BAST_CPLD_CTRL1_LRCADC (0x01)
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#define BAST_CPLD_CTRL1_LRCDAC (0x02)
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#define BAST_CPLD_CTRL1_LRCARM (0x03)
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#define BAST_CPLD_CTRL1_LRMASK (0x03)
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/* CTRL2 - NAND WP control, IDE Reset assert/check */
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#define BAST_CPLD_CTRL2_WNAND (0x04)
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#define BAST_CPLD_CTLR2_IDERST (0x08)
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/* CTRL3 - rom write control, CPLD identity */
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#define BAST_CPLD_CTRL3_IDMASK (0x0e)
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#define BAST_CPLD_CTRL3_ROMWEN (0x01)
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/* CTRL4 - 8bit LCD interface control/status */
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#define BAST_CPLD_CTRL4_LLAT (0x01)
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#define BAST_CPLD_CTRL4_LCDRW (0x02)
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#define BAST_CPLD_CTRL4_LCDCMD (0x04)
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#define BAST_CPLD_CTRL4_LCDE2 (0x01)
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/* CTRL5 - DMA routing */
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#define BAST_CPLD_DMA0_PRIIDE (0<<0)
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#define BAST_CPLD_DMA0_SECIDE (1<<0)
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#define BAST_CPLD_DMA0_ISA15 (2<<0)
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#define BAST_CPLD_DMA0_ISA36 (3<<0)
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#define BAST_CPLD_DMA1_PRIIDE (0<<2)
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#define BAST_CPLD_DMA1_SECIDE (1<<2)
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#define BAST_CPLD_DMA1_ISA15 (2<<2)
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#define BAST_CPLD_DMA1_ISA36 (3<<2)
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#endif /* __ASM_ARCH_BASTCPLD_H */
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