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51 lines
1.9 KiB
51 lines
1.9 KiB
13 years ago
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/*
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* arch/arm/mach-ep93xx/soc.h
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*
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* Copyright (C) 2012 Open Kernel Labs <www.ok-labs.com>
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* Copyright (C) 2012 Ryan Mallon <rmallon@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#ifndef _EP93XX_SOC_H
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#define _EP93XX_SOC_H
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/*
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* EP93xx Physical Memory Map:
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*
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* The ASDO pin is sampled at system reset to select a synchronous or
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* asynchronous boot configuration. When ASDO is "1" (i.e. pulled-up)
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* the synchronous boot mode is selected. When ASDO is "0" (i.e
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* pulled-down) the asynchronous boot mode is selected.
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*
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* In synchronous boot mode nSDCE3 is decoded starting at physical address
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* 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
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* boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
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* decoded at 0xf0000000.
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*
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* There is known errata for the EP93xx dealing with External Memory
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* Configurations. Please refer to "AN273: EP93xx Silicon Rev E Design
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* Guidelines" for more information. This document can be found at:
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*
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* http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
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*/
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#define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
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#define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
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#define EP93XX_CS1_PHYS_BASE 0x10000000
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#define EP93XX_CS2_PHYS_BASE 0x20000000
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#define EP93XX_CS3_PHYS_BASE 0x30000000
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#define EP93XX_PCMCIA_PHYS_BASE 0x40000000
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#define EP93XX_CS6_PHYS_BASE 0x60000000
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#define EP93XX_CS7_PHYS_BASE 0x70000000
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#define EP93XX_SDCE0_PHYS_BASE 0xc0000000
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#define EP93XX_SDCE1_PHYS_BASE 0xd0000000
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#define EP93XX_SDCE2_PHYS_BASE 0xe0000000
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#define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin = 0 */
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#define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin = 1 */
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#endif /* _EP93XX_SOC_H */
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