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/*
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* arch/arm/plat-orion/irq.c
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*
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* Marvell Orion SoC IRQ handling.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <plat/irq.h>
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static void orion_irq_mask(u32 irq)
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{
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void __iomem *maskaddr = get_irq_chip_data(irq);
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u32 mask;
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mask = readl(maskaddr);
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mask &= ~(1 << (irq & 31));
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writel(mask, maskaddr);
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}
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static void orion_irq_unmask(u32 irq)
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{
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void __iomem *maskaddr = get_irq_chip_data(irq);
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u32 mask;
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mask = readl(maskaddr);
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mask |= 1 << (irq & 31);
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writel(mask, maskaddr);
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}
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static struct irq_chip orion_irq_chip = {
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.name = "orion_irq",
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.mask = orion_irq_mask,
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.mask_ack = orion_irq_mask,
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.unmask = orion_irq_unmask,
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};
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void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
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{
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unsigned int i;
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/*
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* Mask all interrupts initially.
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*/
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writel(0, maskaddr);
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/*
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* Register IRQ sources.
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*/
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for (i = 0; i < 32; i++) {
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unsigned int irq = irq_start + i;
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set_irq_chip(irq, &orion_irq_chip);
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set_irq_chip_data(irq, maskaddr);
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set_irq_handler(irq, handle_level_irq);
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irq_desc[irq].status |= IRQ_LEVEL;
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set_irq_flags(irq, IRQF_VALID);
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}
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}
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