[PATCH] avr32 architecture
This adds support for the Atmel AVR32 architecture as well as the AT32AP7000
CPU and the AT32STK1000 development board.
AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for
cost-sensitive embedded applications, with particular emphasis on low power
consumption and high code density. The AVR32 architecture is not binary
compatible with earlier 8-bit AVR architectures.
The AVR32 architecture, including the instruction set, is described by the
AVR32 Architecture Manual, available from
http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf
The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It
features a 7-stage pipeline, 16KB instruction and data caches and a full
Memory Management Unit. It also comes with a large set of integrated
peripherals, many of which are shared with the AT91 ARM-based controllers from
Atmel.
Full data sheet is available from
http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf
while the CPU core implementation including caches and MMU is documented by
the AVR32 AP Technical Reference, available from
http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf
Information about the AT32STK1000 development board can be found at
http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918
including a BSP CD image with an earlier version of this patch, development
tools (binaries and source/patches) and a root filesystem image suitable for
booting from SD card.
Alternatively, there's a preliminary "getting started" guide available at
http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links
to the sources and patches you will need in order to set up a cross-compiling
environment for avr32-linux.
This patch, as well as the other patches included with the BSP and the
toolchain patches, is actively supported by Atmel Corporation.
[dmccr@us.ibm.com: Fix more pxx_page macro locations]
[bunk@stusta.de: fix `make defconfig']
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Dave McCracken <dmccr@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
19 years ago
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/*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/dma-mapping.h>
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#include <asm/addrspace.h>
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#include <asm/cacheflush.h>
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void dma_cache_sync(struct device *dev, void *vaddr, size_t size, int direction)
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[PATCH] avr32 architecture
This adds support for the Atmel AVR32 architecture as well as the AT32AP7000
CPU and the AT32STK1000 development board.
AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for
cost-sensitive embedded applications, with particular emphasis on low power
consumption and high code density. The AVR32 architecture is not binary
compatible with earlier 8-bit AVR architectures.
The AVR32 architecture, including the instruction set, is described by the
AVR32 Architecture Manual, available from
http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf
The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It
features a 7-stage pipeline, 16KB instruction and data caches and a full
Memory Management Unit. It also comes with a large set of integrated
peripherals, many of which are shared with the AT91 ARM-based controllers from
Atmel.
Full data sheet is available from
http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf
while the CPU core implementation including caches and MMU is documented by
the AVR32 AP Technical Reference, available from
http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf
Information about the AT32STK1000 development board can be found at
http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918
including a BSP CD image with an earlier version of this patch, development
tools (binaries and source/patches) and a root filesystem image suitable for
booting from SD card.
Alternatively, there's a preliminary "getting started" guide available at
http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links
to the sources and patches you will need in order to set up a cross-compiling
environment for avr32-linux.
This patch, as well as the other patches included with the BSP and the
toolchain patches, is actively supported by Atmel Corporation.
[dmccr@us.ibm.com: Fix more pxx_page macro locations]
[bunk@stusta.de: fix `make defconfig']
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Dave McCracken <dmccr@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
19 years ago
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{
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/*
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* No need to sync an uncached area
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*/
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if (PXSEG(vaddr) == P2SEG)
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return;
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switch (direction) {
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case DMA_FROM_DEVICE: /* invalidate only */
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dma_cache_inv(vaddr, size);
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break;
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case DMA_TO_DEVICE: /* writeback only */
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dma_cache_wback(vaddr, size);
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break;
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case DMA_BIDIRECTIONAL: /* writeback and invalidate */
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dma_cache_wback_inv(vaddr, size);
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break;
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default:
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BUG();
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}
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}
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EXPORT_SYMBOL(dma_cache_sync);
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static struct page *__dma_alloc(struct device *dev, size_t size,
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dma_addr_t *handle, gfp_t gfp)
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{
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struct page *page, *free, *end;
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int order;
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size = PAGE_ALIGN(size);
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order = get_order(size);
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page = alloc_pages(gfp, order);
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if (!page)
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return NULL;
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split_page(page, order);
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/*
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* When accessing physical memory with valid cache data, we
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* get a cache hit even if the virtual memory region is marked
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* as uncached.
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*
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* Since the memory is newly allocated, there is no point in
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* doing a writeback. If the previous owner cares, he should
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* have flushed the cache before releasing the memory.
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*/
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invalidate_dcache_region(phys_to_virt(page_to_phys(page)), size);
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*handle = page_to_bus(page);
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free = page + (size >> PAGE_SHIFT);
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end = page + (1 << order);
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/*
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* Free any unused pages
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*/
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while (free < end) {
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__free_page(free);
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free++;
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}
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return page;
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}
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static void __dma_free(struct device *dev, size_t size,
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struct page *page, dma_addr_t handle)
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{
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struct page *end = page + (PAGE_ALIGN(size) >> PAGE_SHIFT);
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while (page < end)
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__free_page(page++);
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}
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void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *handle, gfp_t gfp)
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{
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struct page *page;
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void *ret = NULL;
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page = __dma_alloc(dev, size, handle, gfp);
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if (page)
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ret = phys_to_uncached(page_to_phys(page));
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return ret;
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}
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EXPORT_SYMBOL(dma_alloc_coherent);
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void dma_free_coherent(struct device *dev, size_t size,
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void *cpu_addr, dma_addr_t handle)
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{
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void *addr = phys_to_cached(uncached_to_phys(cpu_addr));
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struct page *page;
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pr_debug("dma_free_coherent addr %p (phys %08lx) size %u\n",
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cpu_addr, (unsigned long)handle, (unsigned)size);
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BUG_ON(!virt_addr_valid(addr));
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page = virt_to_page(addr);
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__dma_free(dev, size, page, handle);
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}
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EXPORT_SYMBOL(dma_free_coherent);
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#if 0
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void *dma_alloc_writecombine(struct device *dev, size_t size,
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dma_addr_t *handle, gfp_t gfp)
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{
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struct page *page;
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page = __dma_alloc(dev, size, handle, gfp);
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/* Now, map the page into P3 with write-combining turned on */
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return __ioremap(page_to_phys(page), size, _PAGE_BUFFER);
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}
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EXPORT_SYMBOL(dma_alloc_writecombine);
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void dma_free_writecombine(struct device *dev, size_t size,
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void *cpu_addr, dma_addr_t handle)
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{
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struct page *page;
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iounmap(cpu_addr);
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page = bus_to_page(handle);
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__dma_free(dev, size, page, handle);
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}
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EXPORT_SYMBOL(dma_free_writecombine);
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#endif
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