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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_ATOLL_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_ATOLL_H
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/* Dummy clocks for rate measurement */
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#define MEASURE_ONLY_BIMC_CLK 0
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#define MEASURE_ONLY_CNOC_CLK 1
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#define MEASURE_ONLY_IPA_2X_CLK 2
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#define MEASURE_ONLY_SNOC_CLK 3
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#define GCC_GPLL0_MAIN_DIV_CDIV 4
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/* GCC clocks */
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#define GPLL0 5
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#define GPLL0_OUT_EVEN 6
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#define GPLL6 7
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#define GPLL7 8
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#define GCC_AGGRE_UFS_PHY_AXI_CLK 9
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#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 10
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 11
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#define GCC_BOOT_ROM_AHB_CLK 12
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#define GCC_CAMERA_AHB_CLK 13
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#define GCC_CAMERA_HF_AXI_CLK 14
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#define GCC_CAMERA_THROTTLE_HF_AXI_CLK 15
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#define GCC_CAMERA_XO_CLK 16
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#define GCC_CE1_AHB_CLK 17
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#define GCC_CE1_AXI_CLK 18
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#define GCC_CE1_CLK 19
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 20
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#define GCC_CPUSS_AHB_CLK 21
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#define GCC_CPUSS_AHB_CLK_SRC 22
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#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 23
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#define GCC_CPUSS_GNOC_CLK 24
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#define GCC_CPUSS_RBCPR_CLK 25
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#define GCC_DDRSS_GPU_AXI_CLK 26
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#define GCC_DISP_AHB_CLK 27
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#define GCC_DISP_GPLL0_CLK_SRC 28
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#define GCC_DISP_GPLL0_DIV_CLK_SRC 29
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#define GCC_DISP_HF_AXI_CLK 30
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#define GCC_DISP_THROTTLE_HF_AXI_CLK 31
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#define GCC_DISP_XO_CLK 32
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#define GCC_GP1_CLK 33
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#define GCC_GP1_CLK_SRC 34
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#define GCC_GP2_CLK 35
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#define GCC_GP2_CLK_SRC 36
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#define GCC_GP3_CLK 37
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#define GCC_GP3_CLK_SRC 38
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#define GCC_GPU_CFG_AHB_CLK 39
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#define GCC_GPU_GPLL0_CLK_SRC 40
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 41
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#define GCC_GPU_MEMNOC_GFX_CLK 42
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#define GCC_GPU_SNOC_DVM_GFX_CLK 43
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#define GCC_NPU_AXI_CLK 44
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#define GCC_NPU_BWMON_AXI_CLK 45
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#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 46
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#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 47
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#define GCC_NPU_CFG_AHB_CLK 48
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#define GCC_NPU_DMA_CLK 49
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#define GCC_NPU_GPLL0_CLK_SRC 50
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#define GCC_NPU_GPLL0_DIV_CLK_SRC 51
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#define GCC_PDM2_CLK 52
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#define GCC_PDM2_CLK_SRC 53
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#define GCC_PDM_AHB_CLK 54
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#define GCC_PDM_XO4_CLK 55
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#define GCC_PRNG_AHB_CLK 56
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#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 57
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#define GCC_QSPI_CORE_CLK 58
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#define GCC_QSPI_CORE_CLK_SRC 59
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 60
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#define GCC_QUPV3_WRAP0_CORE_CLK 61
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#define GCC_QUPV3_WRAP0_S0_CLK 62
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 63
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#define GCC_QUPV3_WRAP0_S1_CLK 64
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 65
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#define GCC_QUPV3_WRAP0_S2_CLK 66
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 67
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#define GCC_QUPV3_WRAP0_S3_CLK 68
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 69
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#define GCC_QUPV3_WRAP0_S4_CLK 70
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 71
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#define GCC_QUPV3_WRAP0_S5_CLK 72
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 73
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 74
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#define GCC_QUPV3_WRAP1_CORE_CLK 75
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#define GCC_QUPV3_WRAP1_S0_CLK 76
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 77
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#define GCC_QUPV3_WRAP1_S1_CLK 78
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 79
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#define GCC_QUPV3_WRAP1_S2_CLK 80
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 81
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#define GCC_QUPV3_WRAP1_S3_CLK 82
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 83
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#define GCC_QUPV3_WRAP1_S4_CLK 84
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 85
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#define GCC_QUPV3_WRAP1_S5_CLK 86
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 87
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 88
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 89
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 90
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 91
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#define GCC_SDCC1_AHB_CLK 92
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#define GCC_SDCC1_APPS_CLK 93
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#define GCC_SDCC1_APPS_CLK_SRC 94
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#define GCC_SDCC1_ICE_CORE_CLK 95
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#define GCC_SDCC1_ICE_CORE_CLK_SRC 96
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#define GCC_SDCC2_AHB_CLK 97
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#define GCC_SDCC2_APPS_CLK 98
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#define GCC_SDCC2_APPS_CLK_SRC 99
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 100
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#define GCC_UFS_MEM_CLKREF_CLK 101
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#define GCC_UFS_PHY_AHB_CLK 102
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#define GCC_UFS_PHY_AXI_CLK 103
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#define GCC_UFS_PHY_AXI_CLK_SRC 104
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#define GCC_UFS_PHY_AXI_HW_CTL_CLK 105
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#define GCC_UFS_PHY_ICE_CORE_CLK 106
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 107
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#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 108
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#define GCC_UFS_PHY_PHY_AUX_CLK 109
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 110
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#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 111
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 112
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 113
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 114
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 115
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#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 116
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#define GCC_USB30_PRIM_MASTER_CLK 117
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 118
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 119
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 120
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#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 121
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#define GCC_USB30_PRIM_SLEEP_CLK 122
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#define GCC_USB3_PRIM_CLKREF_CLK 123
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#define GCC_USB3_PRIM_PHY_AUX_CLK 124
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 125
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 126
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 127
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#define GCC_USB_PHY_CFG_AHB2PHY_CLK 128
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#define GCC_VIDEO_AHB_CLK 129
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#define GCC_VIDEO_AXI_CLK 130
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#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 131
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#define GCC_VIDEO_THROTTLE_AXI_CLK 132
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#define GCC_VIDEO_XO_CLK 133
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/* GCC resets */
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#define GCC_QUSB2PHY_PRIM_BCR 0
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#define GCC_QUSB2PHY_SEC_BCR 1
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#define GCC_UFS_PHY_BCR 2
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#define GCC_USB30_PRIM_BCR 3
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#define GCC_USB3_DP_PHY_PRIM_BCR 4
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#define GCC_USB3_DP_PHY_SEC_BCR 5
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#define GCC_USB3_PHY_PRIM_BCR 6
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#define GCC_USB3_PHY_SEC_BCR 7
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#define GCC_USB3PHY_PHY_PRIM_BCR 8
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#define GCC_USB3PHY_PHY_SEC_BCR 9
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10
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#endif
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