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123 lines
3.7 KiB
123 lines
3.7 KiB
5 years ago
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/* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef MDSS_DSI_PLL_12NM_H
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#define MDSS_DSI_PLL_12NM_H
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#define DSIPHY_PLL_POWERUP_CTRL 0x034
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#define DSIPHY_PLL_PROP_CHRG_PUMP_CTRL 0x038
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#define DSIPHY_PLL_INTEG_CHRG_PUMP_CTRL 0x03c
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#define DSIPHY_PLL_ANA_TST_LOCK_ST_OVR_CTRL 0x044
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#define DSIPHY_PLL_VCO_CTRL 0x048
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#define DSIPHY_PLL_GMP_CTRL_DIG_TST 0x04c
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#define DSIPHY_PLL_PHA_ERR_CTRL_0 0x050
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#define DSIPHY_PLL_LOCK_FILTER 0x054
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#define DSIPHY_PLL_UNLOCK_FILTER 0x058
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#define DSIPHY_PLL_INPUT_DIV_PLL_OVR 0x05c
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#define DSIPHY_PLL_LOOP_DIV_RATIO_0 0x060
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#define DSIPHY_PLL_INPUT_LOOP_DIV_RAT_CTRL 0x064
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#define DSIPHY_PLL_PRO_DLY_RELOCK 0x06c
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#define DSIPHY_PLL_CHAR_PUMP_BIAS_CTRL 0x070
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#define DSIPHY_PLL_LOCK_DET_MODE_SEL 0x074
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#define DSIPHY_PLL_ANA_PROG_CTRL 0x07c
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#define DSIPHY_HS_FREQ_RAN_SEL 0x110
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#define DSIPHY_SLEWRATE_FSM_OVR_CTRL 0x280
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#define DSIPHY_SLEWRATE_DDL_LOOP_CTRL 0x28c
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#define DSIPHY_SLEWRATE_DDL_CYC_FRQ_ADJ_0 0x290
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#define DSIPHY_PLL_PHA_ERR_CTRL_1 0x2e4
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#define DSIPHY_PLL_LOOP_DIV_RATIO_1 0x2e8
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#define DSIPHY_SLEWRATE_DDL_CYC_FRQ_ADJ_1 0x328
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#define DSIPHY_SSC0 0x394
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#define DSIPHY_SSC7 0x3b0
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#define DSIPHY_SSC8 0x3b4
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#define DSIPHY_SSC1 0x398
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#define DSIPHY_SSC2 0x39c
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#define DSIPHY_SSC3 0x3a0
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#define DSIPHY_SSC4 0x3a4
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#define DSIPHY_SSC5 0x3a8
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#define DSIPHY_SSC6 0x3ac
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#define DSIPHY_SSC10 0x360
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#define DSIPHY_SSC11 0x364
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#define DSIPHY_SSC12 0x368
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#define DSIPHY_SSC13 0x36c
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#define DSIPHY_SSC14 0x370
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#define DSIPHY_SSC15 0x374
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#define DSIPHY_SSC7 0x3b0
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#define DSIPHY_SSC8 0x3b4
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#define DSIPHY_SSC9 0x3b8
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#define DSIPHY_STAT0 0x3e0
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#define DSIPHY_CTRL0 0x3e8
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#define DSIPHY_SYS_CTRL 0x3f0
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#define DSIPHY_PLL_CTRL 0x3f8
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struct dsi_pll_param {
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u32 hsfreqrange;
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u32 vco_cntrl;
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u32 osc_freq_target;
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u32 m_div;
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u32 prop_cntrl;
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u32 int_cntrl;
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u32 gmp_cntrl;
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u32 cpbias_cntrl;
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/* mux and dividers */
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u32 gp_div_mux;
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u32 post_div_mux;
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u32 pixel_divhf;
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u32 fsm_ovr_ctrl;
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/* ssc_params */
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u32 mpll_ssc_peak_i;
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u32 mpll_stepsize_i;
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u32 mpll_mint_i;
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u32 mpll_frac_den;
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u32 mpll_frac_quot_i;
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u32 mpll_frac_rem;
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};
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enum {
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DSI_PLL_0,
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DSI_PLL_1,
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DSI_PLL_MAX
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};
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struct dsi_pll_db {
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struct dsi_pll_db *next;
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struct mdss_pll_resources *pll;
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struct dsi_pll_param param;
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};
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int pll_vco_set_rate_12nm(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate);
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long pll_vco_round_rate_12nm(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate);
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unsigned long vco_12nm_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate);
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int pll_vco_prepare_12nm(struct clk_hw *hw);
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void pll_vco_unprepare_12nm(struct clk_hw *hw);
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int pll_vco_enable_12nm(struct clk_hw *hw);
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int pixel_div_set_div(void *context, unsigned int reg,
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unsigned int div);
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int pixel_div_get_div(void *context, unsigned int reg,
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unsigned int *div);
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int set_post_div_mux_sel(void *context, unsigned int reg,
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unsigned int sel);
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int get_post_div_mux_sel(void *context, unsigned int reg,
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unsigned int *sel);
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int set_gp_mux_sel(void *context, unsigned int reg,
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unsigned int sel);
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int get_gp_mux_sel(void *context, unsigned int reg,
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unsigned int *sel);
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int dsi_pll_enable_seq_12nm(struct mdss_pll_resources *pll);
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#endif /* MDSS_DSI_PLL_12NM_H */
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