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/*
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* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "clk: %s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/clock/qcom,gpucc-sdmmagpie.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "common.h"
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#include "reset.h"
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#include "vdd-level-sdmmagpie.h"
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#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
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enum vdd_gx_levels {
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VDD_GX_NONE,
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VDD_GX_MIN, /* MIN SVS */
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VDD_GX_LOWER, /* SVS2 */
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VDD_GX_LOW, /* SVS */
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VDD_GX_LOW_L1, /* SVSL1 */
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VDD_GX_NOMINAL, /* NOM */
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VDD_GX_NOMINAL_L1, /* NOM1 */
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VDD_GX_HIGH, /* TURBO */
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VDD_GX_HIGH_L1, /* TURBO1 */
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VDD_GX_NUM,
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};
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static int vdd_gx_corner[] = {
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RPMH_REGULATOR_LEVEL_OFF, /* VDD_GX_NONE */
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RPMH_REGULATOR_LEVEL_MIN_SVS, /* VDD_GX_MIN */
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RPMH_REGULATOR_LEVEL_LOW_SVS, /* VDD_GX_LOWER */
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RPMH_REGULATOR_LEVEL_SVS, /* VDD_GX_LOW */
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RPMH_REGULATOR_LEVEL_SVS_L1, /* VDD_GX_LOW_L1 */
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RPMH_REGULATOR_LEVEL_NOM, /* VDD_GX_NOMINAL */
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RPMH_REGULATOR_LEVEL_NOM_L1, /* VDD_GX_NOMINAL_L1 */
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RPMH_REGULATOR_LEVEL_TURBO, /* VDD_GX_HIGH */
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RPMH_REGULATOR_LEVEL_TURBO_L1, /* VDD_GX_HIGH_L1 */
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RPMH_REGULATOR_LEVEL_MAX, /* VDD_GX_MAX */
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};
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static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
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static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner);
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static DEFINE_VDD_REGULATORS(vdd_gx, VDD_GX_NUM, 1, vdd_gx_corner);
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#define CX_GMU_CBCR_SLEEP_MASK 0xF
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#define CX_GMU_CBCR_SLEEP_SHIFT 4
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#define CX_GMU_CBCR_WAKE_MASK 0xF
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#define CX_GMU_CBCR_WAKE_SHIFT 8
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enum {
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P_BI_TCXO,
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P_CORE_BI_PLL_TEST_SE,
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P_GPLL0_OUT_MAIN,
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P_GPLL0_OUT_MAIN_DIV,
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P_GPU_CC_PLL0_OUT_EVEN,
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P_GPU_CC_PLL0_OUT_MAIN,
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P_GPU_CC_PLL0_OUT_ODD,
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P_GPU_CC_PLL1_OUT_EVEN,
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P_GPU_CC_PLL1_OUT_MAIN,
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P_GPU_CC_PLL1_OUT_ODD,
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P_CRC_DIV,
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};
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static const struct parent_map gpu_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
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{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gpu_cc_parent_names_0[] = {
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"bi_tcxo",
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"gpu_cc_pll0",
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"gpu_cc_pll1",
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"gcc_gpu_gpll0_clk_src",
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"gcc_gpu_gpll0_div_clk_src",
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"core_bi_pll_test_se",
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};
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static const struct parent_map gpu_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_EVEN, 1 },
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{ P_GPU_CC_PLL0_OUT_ODD, 2 },
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{ P_GPU_CC_PLL1_OUT_EVEN, 3 },
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{ P_GPU_CC_PLL1_OUT_ODD, 4 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gpu_cc_parent_names_1[] = {
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"bi_tcxo",
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"gpu_cc_pll0_out_even",
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"gpu_cc_pll0_out_odd",
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"gpu_cc_pll1_out_even",
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"gpu_cc_pll1_out_odd",
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"gcc_gpu_gpll0_clk_src",
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"core_bi_pll_test_se",
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};
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static const struct parent_map gpu_cc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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{ P_CRC_DIV, 1 },
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{ P_GPU_CC_PLL0_OUT_ODD, 2 },
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{ P_GPU_CC_PLL1_OUT_EVEN, 3 },
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{ P_GPU_CC_PLL1_OUT_ODD, 4 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gpu_cc_parent_names_2[] = {
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"bi_tcxo",
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"crc_div",
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"gpu_cc_pll0_out_odd",
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"gpu_cc_pll1_out_even",
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"gpu_cc_pll1_out_odd",
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"gcc_gpu_gpll0_clk_src",
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"core_bi_pll_test_se",
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};
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static struct pll_vco fabia_vco[] = {
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{ 249600000, 2000000000, 0 },
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{ 125000000, 1000000000, 1 },
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};
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static const struct alpha_pll_config gpu_cc_pll0_config = {
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.l = 0x12,
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.alpha = 0xC000,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002067,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00004805,
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.test_ctl_hi_val = 0x40000000,
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};
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static struct clk_alpha_pll gpu_cc_pll0 = {
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.offset = 0x0,
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.vco_table = fabia_vco,
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.num_vco = ARRAY_SIZE(fabia_vco),
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.type = FABIA_PLL,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll0",
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.parent_names = (const char *[]){ "bi_tcxo" },
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.num_parents = 1,
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.ops = &clk_fabia_pll_ops,
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.vdd_class = &vdd_mx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1600000000,
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[VDD_NOMINAL] = 2000000000},
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},
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},
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};
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static const struct clk_div_table post_div_table_fabia_even[] = {
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{ 0x0, 1 },
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{ 0x1, 2 },
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{ 0x3, 4 },
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{ 0x7, 8 },
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{ }
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};
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static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even = {
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.offset = 0x0,
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.post_div_shift = 8,
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.post_div_table = post_div_table_fabia_even,
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.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
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.width = 4,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll0_out_even",
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.parent_names = (const char *[]){ "gpu_cc_pll0" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_generic_pll_postdiv_ops,
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},
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};
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static struct clk_fixed_factor crc_div = {
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.mult = 1,
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.div = 1,
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.hw.init = &(struct clk_init_data){
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.name = "crc_div",
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.parent_names = (const char *[]){ "gpu_cc_pll0_out_even" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_fixed_factor_ops,
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},
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};
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static struct clk_alpha_pll gpu_cc_pll1 = {
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.offset = 0x100,
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.vco_table = fabia_vco,
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.num_vco = ARRAY_SIZE(fabia_vco),
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.type = FABIA_PLL,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll1",
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.parent_names = (const char *[]){ "bi_tcxo" },
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.num_parents = 1,
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.ops = &clk_fabia_pll_ops,
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.vdd_class = &vdd_mx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1600000000,
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[VDD_NOMINAL] = 2000000000},
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},
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},
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};
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static struct clk_alpha_pll_postdiv gpu_cc_pll1_out_even = {
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.offset = 0x100,
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.post_div_shift = 8,
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.post_div_table = post_div_table_fabia_even,
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.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
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.width = 4,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll1_out_even",
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.parent_names = (const char *[]){ "gpu_cc_pll1" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_generic_pll_postdiv_ops,
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},
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};
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static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpu_cc_gmu_clk_src = {
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.cmd_rcgr = 0x1120,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_0,
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.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gmu_clk_src",
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.parent_names = gpu_cc_parent_names_0,
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.num_parents = 6,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 200000000},
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},
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};
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static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
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F(180000000, P_CRC_DIV, 1, 0, 0),
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F(267000000, P_CRC_DIV, 1, 0, 0),
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F(355000000, P_CRC_DIV, 1, 0, 0),
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F(430000000, P_CRC_DIV, 1, 0, 0),
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F(504000000, P_CRC_DIV, 1, 0, 0),
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F(565000000, P_CRC_DIV, 1, 0, 0),
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F(610000000, P_CRC_DIV, 1, 0, 0),
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F(650000000, P_CRC_DIV, 1, 0, 0),
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F(700000000, P_CRC_DIV, 1, 0, 0),
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F(750000000, P_CRC_DIV, 1, 0, 0),
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F(800000000, P_CRC_DIV, 1, 0, 0),
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F(825000000, P_CRC_DIV, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
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.cmd_rcgr = 0x101c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_2,
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.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
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.flags = FORCE_ENABLE_RCG,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gx_gfx3d_clk_src",
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.parent_names = gpu_cc_parent_names_2,
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.num_parents = 7,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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.vdd_class = &vdd_gx,
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.num_rate_max = VDD_GX_NUM,
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.rate_max = (unsigned long[VDD_GX_NUM]) {
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[VDD_GX_MIN] = 180000000,
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[VDD_GX_LOWER] = 267000000,
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[VDD_GX_LOW] = 355000000,
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[VDD_GX_LOW_L1] = 430000000,
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[VDD_GX_NOMINAL] = 565000000,
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[VDD_GX_NOMINAL_L1] = 650000000,
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[VDD_GX_HIGH] = 800000000,
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[VDD_GX_HIGH_L1] = 825000000},
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},
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};
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static struct clk_branch gpu_cc_acd_ahb_clk = {
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.halt_reg = 0x1168,
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.halt_check = BRANCH_HALT,
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.clkr = {
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|
|
|
.enable_reg = 0x1168,
|
|
|
|
.enable_mask = BIT(0),
|
|
|
|
.hw.init = &(struct clk_init_data){
|
|
|
|
.name = "gpu_cc_acd_ahb_clk",
|
|
|
|
.ops = &clk_branch2_ops,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk_branch gpu_cc_acd_cxo_clk = {
|
|
|
|
.halt_reg = 0x1164,
|
|
|
|
.halt_check = BRANCH_HALT,
|
|
|
|
.clkr = {
|
|
|
|
.enable_reg = 0x1164,
|
|
|
|
.enable_mask = BIT(0),
|
|
|
|
.hw.init = &(struct clk_init_data){
|
|
|
|
.name = "gpu_cc_acd_cxo_clk",
|
|
|
|
.ops = &clk_branch2_ops,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk_branch gpu_cc_ahb_clk = {
|
|
|
|
.halt_reg = 0x1078,
|
|
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
|
|
.clkr = {
|
|
|
|
.enable_reg = 0x1078,
|
|
|
|
.enable_mask = BIT(0),
|
|
|
|
.hw.init = &(struct clk_init_data){
|
|
|
|
.name = "gpu_cc_ahb_clk",
|
|
|
|
.flags = CLK_IS_CRITICAL,
|
|
|
|
.ops = &clk_branch2_ops,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk_branch gpu_cc_crc_ahb_clk = {
|
|
|
|
.halt_reg = 0x107c,
|
|
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
|
|
.clkr = {
|
|
|
|
.enable_reg = 0x107c,
|
|
|
|
.enable_mask = BIT(0),
|
|
|
|
.hw.init = &(struct clk_init_data){
|
|
|
|
.name = "gpu_cc_crc_ahb_clk",
|
|
|
|
.ops = &clk_branch2_ops,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk_branch gpu_cc_cx_apb_clk = {
|
|
|
|
.halt_reg = 0x1088,
|
|
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
|
|
.clkr = {
|
|
|
|
.enable_reg = 0x1088,
|
|
|
|
.enable_mask = BIT(0),
|
|
|
|
.hw.init = &(struct clk_init_data){
|
|
|
|
.name = "gpu_cc_cx_apb_clk",
|
|
|
|
.ops = &clk_branch2_ops,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk_branch gpu_cc_cx_gfx3d_clk = {
|
|
|
|
.halt_reg = 0x10a4,
|
|
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
|
|
.clkr = {
|
|
|
|
.enable_reg = 0x10a4,
|
|
|
|
.enable_mask = BIT(0),
|
|
|
|
.hw.init = &(struct clk_init_data){
|
|
|
|
.name = "gpu_cc_cx_gfx3d_clk",
|
|
|
|
.parent_names = (const char *[]){
|
|
|
|
"gpu_cc_gx_gfx3d_clk_src",
|
|
|
|
},
|
|
|
|
.num_parents = 1,
|
|
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
|
|
.ops = &clk_branch2_ops,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = {
|
|
|
|
.halt_reg = 0x10a8,
|
|
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
|
|
.clkr = {
|
|
|
|
.enable_reg = 0x10a8,
|
|
|
|
.enable_mask = BIT(0),
|
|
|
|
.hw.init = &(struct clk_init_data){
|
|
|
|
.name = "gpu_cc_cx_gfx3d_slv_clk",
|
|
|
|
.parent_names = (const char *[]){
|
|
|
|
"gpu_cc_gx_gfx3d_clk_src",
|
|
|
|
},
|
|
|
|
.num_parents = 1,
|
|
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
|
|
.ops = &clk_branch2_ops,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk_branch gpu_cc_cx_gmu_clk = {
|
|
|
|
.halt_reg = 0x1098,
|
|
|
|
.halt_check = BRANCH_HALT,
|
|
|
|
.clkr = {
|
|
|
|
.enable_reg = 0x1098,
|
|
|
|
.enable_mask = BIT(0),
|
|
|
|
.hw.init = &(struct clk_init_data){
|
|
|
|
.name = "gpu_cc_cx_gmu_clk",
|
|
|
|
.parent_names = (const char *[]){
|
|
|
|
"gpu_cc_gmu_clk_src",
|
|
|
|
},
|
|
|
|
.num_parents = 1,
|
|
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
|
|
.ops = &clk_branch2_ops,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
|
|
|
|
.halt_reg = 0x108c,
|
|
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
|
|
.clkr = {
|
|
|
|
.enable_reg = 0x108c,
|
|
|
|
.enable_mask = BIT(0),
|
|
|
|
.hw.init = &(struct clk_init_data){
|
|
|
|
.name = "gpu_cc_cx_snoc_dvm_clk",
|
|
|
|
.ops = &clk_branch2_ops,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk_branch gpu_cc_cxo_aon_clk = {
|
|
|
|
.halt_reg = 0x1004,
|
|
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
|
|
.clkr = {
|
|
|
|
.enable_reg = 0x1004,
|
|
|
|
.enable_mask = BIT(0),
|
|
|
|
.hw.init = &(struct clk_init_data){
|
|
|
|
.name = "gpu_cc_cxo_aon_clk",
|
|
|
|
.ops = &clk_branch2_ops,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk_branch gpu_cc_cxo_clk = {
|
|
|
|
.halt_reg = 0x109c,
|
|
|
|
.halt_check = BRANCH_HALT,
|
|
|
|
.clkr = {
|
|
|
|
.enable_reg = 0x109c,
|
|
|
|
.enable_mask = BIT(0),
|
|
|
|
.hw.init = &(struct clk_init_data){
|
|
|
|
.name = "gpu_cc_cxo_clk",
|
|
|
|
.ops = &clk_branch2_ops,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk_branch gpu_cc_gx_cxo_clk = {
|
|
|
|
.halt_reg = 0x1060,
|
|
|
|
.halt_check = BRANCH_HALT,
|
|
|
|
.clkr = {
|
|
|
|
.enable_reg = 0x1060,
|
|
|
|
.enable_mask = BIT(0),
|
|
|
|
.hw.init = &(struct clk_init_data){
|
|
|
|
.name = "gpu_cc_gx_cxo_clk",
|
|
|
|
.ops = &clk_branch2_ops,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
|
|
|
|
.halt_reg = 0x1054,
|
|
|
|
.halt_check = BRANCH_HALT_SKIP,
|
|
|
|
.clkr = {
|
|
|
|
.enable_reg = 0x1054,
|
|
|
|
.enable_mask = BIT(0),
|
|
|
|
.hw.init = &(struct clk_init_data){
|
|
|
|
.name = "gpu_cc_gx_gfx3d_clk",
|
|
|
|
.parent_names = (const char *[]){
|
|
|
|
"gpu_cc_gx_gfx3d_clk_src",
|
|
|
|
},
|
|
|
|
.num_parents = 1,
|
|
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
|
|
.ops = &clk_branch2_ops,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk_branch gpu_cc_gx_gmu_clk = {
|
|
|
|
.halt_reg = 0x1064,
|
|
|
|
.halt_check = BRANCH_HALT,
|
|
|
|
.clkr = {
|
|
|
|
.enable_reg = 0x1064,
|
|
|
|
.enable_mask = BIT(0),
|
|
|
|
.hw.init = &(struct clk_init_data){
|
|
|
|
.name = "gpu_cc_gx_gmu_clk",
|
|
|
|
.parent_names = (const char *[]){
|
|
|
|
"gpu_cc_gmu_clk_src",
|
|
|
|
},
|
|
|
|
.num_parents = 1,
|
|
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
|
|
.ops = &clk_branch2_ops,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk_branch gpu_cc_gx_vsense_clk = {
|
|
|
|
.halt_reg = 0x1058,
|
|
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
|
|
.clkr = {
|
|
|
|
.enable_reg = 0x1058,
|
|
|
|
.enable_mask = BIT(0),
|
|
|
|
.hw.init = &(struct clk_init_data){
|
|
|
|
.name = "gpu_cc_gx_vsense_clk",
|
|
|
|
.ops = &clk_branch2_ops,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk_regmap *gpu_cc_sdmmagpie_clocks[] = {
|
|
|
|
[GPU_CC_ACD_AHB_CLK] = &gpu_cc_acd_ahb_clk.clkr,
|
|
|
|
[GPU_CC_ACD_CXO_CLK] = &gpu_cc_acd_cxo_clk.clkr,
|
|
|
|
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
|
|
|
|
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
|
|
|
|
[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
|
|
|
|
[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
|
|
|
|
[GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr,
|
|
|
|
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
|
|
|
|
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
|
|
|
|
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
|
|
|
|
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
|
|
|
|
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
|
|
|
|
[GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,
|
|
|
|
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
|
|
|
|
[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
|
|
|
|
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
|
|
|
|
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
|
|
|
|
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
|
|
|
|
[GPU_CC_PLL0_OUT_EVEN] = &gpu_cc_pll0_out_even.clkr,
|
|
|
|
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
|
|
|
|
[GPU_CC_PLL1_OUT_EVEN] = &gpu_cc_pll1_out_even.clkr,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct regmap_config gpu_cc_sdmmagpie_regmap_config = {
|
|
|
|
.reg_bits = 32,
|
|
|
|
.reg_stride = 4,
|
|
|
|
.val_bits = 32,
|
|
|
|
.max_register = 0x8008,
|
|
|
|
.fast_io = true,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct qcom_cc_desc gpu_cc_sdmmagpie_desc = {
|
|
|
|
.config = &gpu_cc_sdmmagpie_regmap_config,
|
|
|
|
.clks = gpu_cc_sdmmagpie_clocks,
|
|
|
|
.num_clks = ARRAY_SIZE(gpu_cc_sdmmagpie_clocks),
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct of_device_id gpu_cc_sdmmagpie_match_table[] = {
|
|
|
|
{ .compatible = "qcom,gpucc-sdmmagpie" },
|
|
|
|
{ .compatible = "qcom,atoll-gpucc" },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, gpu_cc_sdmmagpie_match_table);
|
|
|
|
|
|
|
|
static int gpu_cc_sdmmagpie_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct regmap *regmap;
|
|
|
|
int ret;
|
|
|
|
unsigned int value, mask;
|
|
|
|
|
|
|
|
/* Get CX voltage regulator for CX and GMU clocks. */
|
|
|
|
vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
|
|
|
|
if (IS_ERR(vdd_cx.regulator[0])) {
|
|
|
|
if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER))
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"Unable to get vdd_cx regulator\n");
|
|
|
|
return PTR_ERR(vdd_cx.regulator[0]);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get MX voltage regulator for GPU PLL graphic clock. */
|
|
|
|
vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx");
|
|
|
|
if (IS_ERR(vdd_mx.regulator[0])) {
|
|
|
|
if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER))
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"Unable to get vdd_mx regulator\n");
|
|
|
|
return PTR_ERR(vdd_mx.regulator[0]);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* GFX voltage regulators for GFX3D graphic clock. */
|
|
|
|
vdd_gx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_gfx");
|
|
|
|
if (IS_ERR(vdd_gx.regulator[0])) {
|
|
|
|
if (PTR_ERR(vdd_gx.regulator[0]) != -EPROBE_DEFER)
|
|
|
|
dev_err(&pdev->dev, "Unable to get vdd_gx regulator\n");
|
|
|
|
return PTR_ERR(vdd_gx.regulator[0]);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Avoid turning on the rail during clock registration */
|
|
|
|
vdd_gx.skip_handoff = true;
|
|
|
|
|
|
|
|
/* Register clock fixed factor for CRC divide. */
|
|
|
|
ret = devm_clk_hw_register(&pdev->dev, &crc_div.hw);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "Failed to register hardware clock\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
regmap = qcom_cc_map(pdev, &gpu_cc_sdmmagpie_desc);
|
|
|
|
if (IS_ERR(regmap)) {
|
|
|
|
pr_err("Failed to map the gpu_cc registers\n");
|
|
|
|
return PTR_ERR(regmap);
|
|
|
|
}
|
|
|
|
|
|
|
|
clk_fabia_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
|
|
|
|
clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll0_config);
|
|
|
|
|
|
|
|
ret = qcom_cc_really_probe(pdev, &gpu_cc_sdmmagpie_desc, regmap);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
|
|
|
|
mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
|
|
|
|
mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
|
|
|
|
value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
|
|
|
|
regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg,
|
|
|
|
mask, value);
|
|
|
|
|
|
|
|
dev_info(&pdev->dev, "Registered GPU CC clocks\n");
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver gpu_cc_sdmmagpie_driver = {
|
|
|
|
.probe = gpu_cc_sdmmagpie_probe,
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|
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.driver = {
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|
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.name = "gpu_cc-sdmmagpie",
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|
|
|
.of_match_table = gpu_cc_sdmmagpie_match_table,
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|
|
|
},
|
|
|
|
};
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|
|
|
|
|
|
|
static int __init gpu_cc_sdmmagpie_init(void)
|
|
|
|
{
|
|
|
|
return platform_driver_register(&gpu_cc_sdmmagpie_driver);
|
|
|
|
}
|
|
|
|
subsys_initcall(gpu_cc_sdmmagpie_init);
|
|
|
|
|
|
|
|
static void __exit gpu_cc_sdmmagpie_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&gpu_cc_sdmmagpie_driver);
|
|
|
|
}
|
|
|
|
module_exit(gpu_cc_sdmmagpie_exit);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("QTI GPU_CC SDMMAGPIE Driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_ALIAS("platform:gpu_cc-sdmmagpie");
|