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212 lines
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212 lines
0 B
20 years ago
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/*
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* linux/include/asm-arm/arch-versatile/irqs.h
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*
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* Copyright (C) 2003 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <asm/arch/platform.h>
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/*
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* IRQ interrupts definitions are the same the INT definitions
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* held within platform.h
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*/
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#define IRQ_VIC_START 0
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#define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT)
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#define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT)
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#define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx)
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#define IRQ_COMMTx (IRQ_VIC_START + INT_COMMTx)
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#define IRQ_TIMERINT0_1 (IRQ_VIC_START + INT_TIMERINT0_1)
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#define IRQ_TIMERINT2_3 (IRQ_VIC_START + INT_TIMERINT2_3)
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#define IRQ_GPIOINT0 (IRQ_VIC_START + INT_GPIOINT0)
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#define IRQ_GPIOINT1 (IRQ_VIC_START + INT_GPIOINT1)
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#define IRQ_GPIOINT2 (IRQ_VIC_START + INT_GPIOINT2)
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#define IRQ_GPIOINT3 (IRQ_VIC_START + INT_GPIOINT3)
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#define IRQ_RTCINT (IRQ_VIC_START + INT_RTCINT)
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#define IRQ_SSPINT (IRQ_VIC_START + INT_SSPINT)
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#define IRQ_UARTINT0 (IRQ_VIC_START + INT_UARTINT0)
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#define IRQ_UARTINT1 (IRQ_VIC_START + INT_UARTINT1)
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#define IRQ_UARTINT2 (IRQ_VIC_START + INT_UARTINT2)
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#define IRQ_SCIINT (IRQ_VIC_START + INT_SCIINT)
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#define IRQ_CLCDINT (IRQ_VIC_START + INT_CLCDINT)
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#define IRQ_DMAINT (IRQ_VIC_START + INT_DMAINT)
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#define IRQ_PWRFAILINT (IRQ_VIC_START + INT_PWRFAILINT)
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#define IRQ_MBXINT (IRQ_VIC_START + INT_MBXINT)
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#define IRQ_GNDINT (IRQ_VIC_START + INT_GNDINT)
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#define IRQ_VICSOURCE21 (IRQ_VIC_START + INT_VICSOURCE21)
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#define IRQ_VICSOURCE22 (IRQ_VIC_START + INT_VICSOURCE22)
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#define IRQ_VICSOURCE23 (IRQ_VIC_START + INT_VICSOURCE23)
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#define IRQ_VICSOURCE24 (IRQ_VIC_START + INT_VICSOURCE24)
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#define IRQ_VICSOURCE25 (IRQ_VIC_START + INT_VICSOURCE25)
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#define IRQ_VICSOURCE26 (IRQ_VIC_START + INT_VICSOURCE26)
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#define IRQ_VICSOURCE27 (IRQ_VIC_START + INT_VICSOURCE27)
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#define IRQ_VICSOURCE28 (IRQ_VIC_START + INT_VICSOURCE28)
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#define IRQ_VICSOURCE29 (IRQ_VIC_START + INT_VICSOURCE29)
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#define IRQ_VICSOURCE30 (IRQ_VIC_START + INT_VICSOURCE30)
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#define IRQ_VICSOURCE31 (IRQ_VIC_START + INT_VICSOURCE31)
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#define IRQ_VIC_END (IRQ_VIC_START + 31)
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#define IRQMASK_WDOGINT INTMASK_WDOGINT
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#define IRQMASK_SOFTINT INTMASK_SOFTINT
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#define IRQMASK_COMMRx INTMASK_COMMRx
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#define IRQMASK_COMMTx INTMASK_COMMTx
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#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
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#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
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#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0
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#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1
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#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2
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#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3
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#define IRQMASK_RTCINT INTMASK_RTCINT
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#define IRQMASK_SSPINT INTMASK_SSPINT
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#define IRQMASK_UARTINT0 INTMASK_UARTINT0
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#define IRQMASK_UARTINT1 INTMASK_UARTINT1
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#define IRQMASK_UARTINT2 INTMASK_UARTINT2
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#define IRQMASK_SCIINT INTMASK_SCIINT
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#define IRQMASK_CLCDINT INTMASK_CLCDINT
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#define IRQMASK_DMAINT INTMASK_DMAINT
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#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT
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#define IRQMASK_MBXINT INTMASK_MBXINT
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#define IRQMASK_GNDINT INTMASK_GNDINT
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#define IRQMASK_VICSOURCE21 INTMASK_VICSOURCE21
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#define IRQMASK_VICSOURCE22 INTMASK_VICSOURCE22
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#define IRQMASK_VICSOURCE23 INTMASK_VICSOURCE23
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#define IRQMASK_VICSOURCE24 INTMASK_VICSOURCE24
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#define IRQMASK_VICSOURCE25 INTMASK_VICSOURCE25
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#define IRQMASK_VICSOURCE26 INTMASK_VICSOURCE26
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#define IRQMASK_VICSOURCE27 INTMASK_VICSOURCE27
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#define IRQMASK_VICSOURCE28 INTMASK_VICSOURCE28
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#define IRQMASK_VICSOURCE29 INTMASK_VICSOURCE29
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#define IRQMASK_VICSOURCE30 INTMASK_VICSOURCE30
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#define IRQMASK_VICSOURCE31 INTMASK_VICSOURCE31
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/*
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* FIQ interrupts definitions are the same the INT definitions.
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*/
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#define FIQ_WDOGINT INT_WDOGINT
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#define FIQ_SOFTINT INT_SOFTINT
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#define FIQ_COMMRx INT_COMMRx
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#define FIQ_COMMTx INT_COMMTx
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#define FIQ_TIMERINT0_1 INT_TIMERINT0_1
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#define FIQ_TIMERINT2_3 INT_TIMERINT2_3
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#define FIQ_GPIOINT0 INT_GPIOINT0
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#define FIQ_GPIOINT1 INT_GPIOINT1
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#define FIQ_GPIOINT2 INT_GPIOINT2
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#define FIQ_GPIOINT3 INT_GPIOINT3
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#define FIQ_RTCINT INT_RTCINT
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#define FIQ_SSPINT INT_SSPINT
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#define FIQ_UARTINT0 INT_UARTINT0
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#define FIQ_UARTINT1 INT_UARTINT1
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#define FIQ_UARTINT2 INT_UARTINT2
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#define FIQ_SCIINT INT_SCIINT
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#define FIQ_CLCDINT INT_CLCDINT
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#define FIQ_DMAINT INT_DMAINT
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#define FIQ_PWRFAILINT INT_PWRFAILINT
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#define FIQ_MBXINT INT_MBXINT
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#define FIQ_GNDINT INT_GNDINT
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#define FIQ_VICSOURCE21 INT_VICSOURCE21
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#define FIQ_VICSOURCE22 INT_VICSOURCE22
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#define FIQ_VICSOURCE23 INT_VICSOURCE23
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#define FIQ_VICSOURCE24 INT_VICSOURCE24
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#define FIQ_VICSOURCE25 INT_VICSOURCE25
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#define FIQ_VICSOURCE26 INT_VICSOURCE26
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#define FIQ_VICSOURCE27 INT_VICSOURCE27
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#define FIQ_VICSOURCE28 INT_VICSOURCE28
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#define FIQ_VICSOURCE29 INT_VICSOURCE29
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#define FIQ_VICSOURCE30 INT_VICSOURCE30
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#define FIQ_VICSOURCE31 INT_VICSOURCE31
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#define FIQMASK_WDOGINT INTMASK_WDOGINT
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#define FIQMASK_SOFTINT INTMASK_SOFTINT
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#define FIQMASK_COMMRx INTMASK_COMMRx
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#define FIQMASK_COMMTx INTMASK_COMMTx
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#define FIQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
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#define FIQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
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#define FIQMASK_GPIOINT0 INTMASK_GPIOINT0
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#define FIQMASK_GPIOINT1 INTMASK_GPIOINT1
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#define FIQMASK_GPIOINT2 INTMASK_GPIOINT2
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#define FIQMASK_GPIOINT3 INTMASK_GPIOINT3
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#define FIQMASK_RTCINT INTMASK_RTCINT
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#define FIQMASK_SSPINT INTMASK_SSPINT
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#define FIQMASK_UARTINT0 INTMASK_UARTINT0
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#define FIQMASK_UARTINT1 INTMASK_UARTINT1
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#define FIQMASK_UARTINT2 INTMASK_UARTINT2
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#define FIQMASK_SCIINT INTMASK_SCIINT
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#define FIQMASK_CLCDINT INTMASK_CLCDINT
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#define FIQMASK_DMAINT INTMASK_DMAINT
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#define FIQMASK_PWRFAILINT INTMASK_PWRFAILINT
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#define FIQMASK_MBXINT INTMASK_MBXINT
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#define FIQMASK_GNDINT INTMASK_GNDINT
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#define FIQMASK_VICSOURCE21 INTMASK_VICSOURCE21
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#define FIQMASK_VICSOURCE22 INTMASK_VICSOURCE22
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#define FIQMASK_VICSOURCE23 INTMASK_VICSOURCE23
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#define FIQMASK_VICSOURCE24 INTMASK_VICSOURCE24
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#define FIQMASK_VICSOURCE25 INTMASK_VICSOURCE25
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#define FIQMASK_VICSOURCE26 INTMASK_VICSOURCE26
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#define FIQMASK_VICSOURCE27 INTMASK_VICSOURCE27
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#define FIQMASK_VICSOURCE28 INTMASK_VICSOURCE28
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#define FIQMASK_VICSOURCE29 INTMASK_VICSOURCE29
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#define FIQMASK_VICSOURCE30 INTMASK_VICSOURCE30
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#define FIQMASK_VICSOURCE31 INTMASK_VICSOURCE31
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/*
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* Secondary interrupt controller
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*/
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#define IRQ_SIC_START 32
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#define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B)
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#define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B)
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#define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0)
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#define IRQ_SIC_KMI1 (IRQ_SIC_START + SIC_INT_KMI1)
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#define IRQ_SIC_SCI3 (IRQ_SIC_START + SIC_INT_SCI3)
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#define IRQ_SIC_UART3 (IRQ_SIC_START + SIC_INT_UART3)
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#define IRQ_SIC_CLCD (IRQ_SIC_START + SIC_INT_CLCD)
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#define IRQ_SIC_TOUCH (IRQ_SIC_START + SIC_INT_TOUCH)
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#define IRQ_SIC_KEYPAD (IRQ_SIC_START + SIC_INT_KEYPAD)
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#define IRQ_SIC_DoC (IRQ_SIC_START + SIC_INT_DoC)
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#define IRQ_SIC_MMCI0A (IRQ_SIC_START + SIC_INT_MMCI0A)
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#define IRQ_SIC_MMCI1A (IRQ_SIC_START + SIC_INT_MMCI1A)
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#define IRQ_SIC_AACI (IRQ_SIC_START + SIC_INT_AACI)
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#define IRQ_SIC_ETH (IRQ_SIC_START + SIC_INT_ETH)
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#define IRQ_SIC_USB (IRQ_SIC_START + SIC_INT_USB)
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#define IRQ_SIC_PCI0 (IRQ_SIC_START + SIC_INT_PCI0)
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#define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1)
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#define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2)
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#define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3)
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#define IRQ_SIC_END 63
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#define SIC_IRQMASK_MMCI0B SIC_INTMASK_MMCI0B
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#define SIC_IRQMASK_MMCI1B SIC_INTMASK_MMCI1B
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#define SIC_IRQMASK_KMI0 SIC_INTMASK_KMI0
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#define SIC_IRQMASK_KMI1 SIC_INTMASK_KMI1
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#define SIC_IRQMASK_SCI3 SIC_INTMASK_SCI3
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#define SIC_IRQMASK_UART3 SIC_INTMASK_UART3
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#define SIC_IRQMASK_CLCD SIC_INTMASK_CLCD
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#define SIC_IRQMASK_TOUCH SIC_INTMASK_TOUCH
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#define SIC_IRQMASK_KEYPAD SIC_INTMASK_KEYPAD
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#define SIC_IRQMASK_DoC SIC_INTMASK_DoC
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#define SIC_IRQMASK_MMCI0A SIC_INTMASK_MMCI0A
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#define SIC_IRQMASK_MMCI1A SIC_INTMASK_MMCI1A
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#define SIC_IRQMASK_AACI SIC_INTMASK_AACI
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#define SIC_IRQMASK_ETH SIC_INTMASK_ETH
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#define SIC_IRQMASK_USB SIC_INTMASK_USB
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#define SIC_IRQMASK_PCI0 SIC_INTMASK_PCI0
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#define SIC_IRQMASK_PCI1 SIC_INTMASK_PCI1
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#define SIC_IRQMASK_PCI2 SIC_INTMASK_PCI2
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#define SIC_IRQMASK_PCI3 SIC_INTMASK_PCI3
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#define NR_IRQS 64
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