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121 lines
3.0 KiB
121 lines
3.0 KiB
20 years ago
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/*
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* arch/mips/ddb5074/int-handler.S -- NEC DDB Vrc-5074 interrupt handler
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*
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* Based on arch/mips/sgi/kernel/indyIRQ.S
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*
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* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
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*
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* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
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* Sony Software Development Center Europe (SDCE), Brussels
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*/
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#include <asm/asm.h>
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#include <asm/mipsregs.h>
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#include <asm/regdef.h>
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#include <asm/stackframe.h>
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/* A lot of complication here is taken away because:
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*
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* 1) We handle one interrupt and return, sitting in a loop and moving across
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* all the pending IRQ bits in the cause register is _NOT_ the answer, the
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* common case is one pending IRQ so optimize in that direction.
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*
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* 2) We need not check against bits in the status register IRQ mask, that
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* would make this routine slow as hell.
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*
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* 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
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* between like BSD spl() brain-damage.
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*
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* Furthermore, the IRQs on the INDY look basically (barring software IRQs
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* which we don't use at all) like:
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*
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* MIPS IRQ Source
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* -------- ------
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* 0 Software (ignored)
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* 1 Software (ignored)
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* 2 Local IRQ level zero
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* 3 Local IRQ level one
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* 4 8254 Timer zero
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* 5 8254 Timer one
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* 6 Bus Error
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* 7 R4k timer (what we use)
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*
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* We handle the IRQ according to _our_ priority which is:
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*
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* Highest ---- R4k Timer
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* Local IRQ zero
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* Local IRQ one
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* Bus Error
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* 8254 Timer zero
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* Lowest ---- 8254 Timer one
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*
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* then we just return, if multiple IRQs are pending then we will just take
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* another exception, big deal.
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*/
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.text
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.set noreorder
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.set noat
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.align 5
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NESTED(ddbIRQ, PT_SIZE, sp)
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SAVE_ALL
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CLI
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.set at
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mfc0 s0, CP0_CAUSE # get irq mask
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#if 1
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mfc0 t2,CP0_STATUS # get enabled interrupts
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and s0,t2 # isolate allowed ones
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#endif
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/* First we check for r4k counter/timer IRQ. */
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andi a0, s0, CAUSEF_IP2 # delay slot, check local level zero
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beq a0, zero, 1f
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andi a0, s0, CAUSEF_IP3 # delay slot, check local level one
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/* Wheee, local level zero interrupt. */
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jal ddb_local0_irqdispatch
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move a0, sp # delay slot
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j ret_from_irq
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nop # delay slot
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1:
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beq a0, zero, 1f
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andi a0, s0, CAUSEF_IP6 # delay slot, check bus error
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/* Wheee, local level one interrupt. */
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move a0, sp
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jal ddb_local1_irqdispatch
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nop
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j ret_from_irq
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nop
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1:
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beq a0, zero, 1f
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nop
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/* Wheee, an asynchronous bus error... */
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move a0, sp
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jal ddb_buserror_irq
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nop
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j ret_from_irq
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nop
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1:
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/* Here by mistake? This is possible, what can happen
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* is that by the time we take the exception the IRQ
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* pin goes low, so just leave if this is the case.
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*/
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andi a0, s0, (CAUSEF_IP4 | CAUSEF_IP5)
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beq a0, zero, 1f
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/* Must be one of the 8254 timers... */
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move a0, sp
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jal ddb_8254timer_irq
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nop
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1:
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j ret_from_irq
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nop
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END(ddbIRQ)
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