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kernel_samsung_sm7125/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi

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arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
/*
* Device Tree Source for UniPhier LD11 SoC
*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
arm64: dts: uniphier: use SPDX-License-Identifier Follow the recent trend for the license description, and fix the wrongly stated X11 to MIT. The X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
*/
arm64: dts: uniphier: reserve more memory for LD11/LD20 Reserve enough space below the kernel base. The assumed address map is: 80000000 - 80ffffff : for IPP 81000000 - 81ffffff : for ARM secure 82000000 - : for Linux Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
/memreserve/ 0x80000000 0x02000000;
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
/ {
compatible = "socionext,uniphier-ld11";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x000>;
arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
8 years ago
clocks = <&sys_clk 33>;
arm64: dts: uniphier: switch over to PSCI enable method At the first system bring-up, I chose to use spin-table because ARM Trusted Firmware was not ready for this platform at that moment. Actually, these SoCs are equipped with EL3 and able to provide PSCI. Now I finished porting the ATF BL31 for the UniPhier platform, so it is ready to migrate to PSCI enable method. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
enable-method = "psci";
arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
8 years ago
operating-points-v2 = <&cluster0_opp>;
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x001>;
arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
8 years ago
clocks = <&sys_clk 33>;
arm64: dts: uniphier: switch over to PSCI enable method At the first system bring-up, I chose to use spin-table because ARM Trusted Firmware was not ready for this platform at that moment. Actually, these SoCs are equipped with EL3 and able to provide PSCI. Now I finished porting the ATF BL31 for the UniPhier platform, so it is ready to migrate to PSCI enable method. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
enable-method = "psci";
arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
8 years ago
operating-points-v2 = <&cluster0_opp>;
};
};
cluster0_opp: opp_table {
compatible = "operating-points-v2";
opp-shared;
arm64: dts: uniphier: Use - instead of @ for DT OPP entries Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
opp-245000000 {
arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
8 years ago
opp-hz = /bits/ 64 <245000000>;
clock-latency-ns = <300>;
};
arm64: dts: uniphier: Use - instead of @ for DT OPP entries Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
opp-250000000 {
arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
8 years ago
opp-hz = /bits/ 64 <250000000>;
clock-latency-ns = <300>;
};
arm64: dts: uniphier: Use - instead of @ for DT OPP entries Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
opp-490000000 {
arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
8 years ago
opp-hz = /bits/ 64 <490000000>;
clock-latency-ns = <300>;
};
arm64: dts: uniphier: Use - instead of @ for DT OPP entries Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
opp-500000000 {
arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
8 years ago
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <300>;
};
arm64: dts: uniphier: Use - instead of @ for DT OPP entries Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
opp-653334000 {
arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
8 years ago
opp-hz = /bits/ 64 <653334000>;
clock-latency-ns = <300>;
};
arm64: dts: uniphier: Use - instead of @ for DT OPP entries Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
opp-666667000 {
arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
8 years ago
opp-hz = /bits/ 64 <666667000>;
clock-latency-ns = <300>;
};
arm64: dts: uniphier: Use - instead of @ for DT OPP entries Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
opp-980000000 {
arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
8 years ago
opp-hz = /bits/ 64 <980000000>;
clock-latency-ns = <300>;
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
};
};
arm64: dts: uniphier: switch over to PSCI enable method At the first system bring-up, I chose to use spin-table because ARM Trusted Firmware was not ready for this platform at that moment. Actually, these SoCs are equipped with EL3 and able to provide PSCI. Now I finished porting the ATF BL31 for the UniPhier platform, so it is ready to migrate to PSCI enable method. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
clocks {
refclk: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>,
<1 14 4>,
<1 11 4>,
<1 10 4>;
};
arm64: dts: uniphier: fix no unit name warnings Fix warnings reported when built with W=1: Node /memory has a reg or ranges property, but no unit name Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
soc@0 {
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
};
serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
};
serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
};
serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 177 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
};
arm64: dts: uniphier: add reset controller node of analog amplifier This patch adds reset controller node of analog signal amplifier core (ADAMV) for UniPhier LD11/LD20 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years ago
adamv@57920000 {
compatible = "socionext,uniphier-ld11-adamv",
"simple-mfd", "syscon";
reg = <0x57920000 0x1000>;
adamv_rst: reset {
compatible = "socionext,uniphier-ld11-adamv-reset";
#reset-cells = <1>;
};
};
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
i2c0: i2c@58780000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
clock-frequency = <100000>;
};
i2c1: i2c@58781000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 42 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
clock-frequency = <100000>;
};
i2c2: i2c@58782000 {
compatible = "socionext,uniphier-fi2c";
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 4>;
clocks = <&peri_clk 6>;
clock-frequency = <400000>;
};
i2c3: i2c@58783000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 44 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
clock-frequency = <100000>;
};
i2c4: i2c@58784000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
reg = <0x58784000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 45 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clocks = <&peri_clk 8>;
clock-frequency = <100000>;
};
i2c5: i2c@58785000 {
compatible = "socionext,uniphier-fi2c";
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 25 4>;
clocks = <&peri_clk 9>;
clock-frequency = <400000>;
};
system_bus: system-bus@58c00000 {
compatible = "socionext,uniphier-system-bus";
status = "disabled";
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_system_bus>;
};
arm64: dts: uniphier: fix simple-bus unit address format error Compiling the UniPhier DT files with W=1, DTC warns like follows: Warning (simple_bus_reg): Node /soc/smpctrl@59800000 simple-bus unit address format error, expected "59801000" Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
smpctrl@59801000 {
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
arm64: dts: uniphier: add SD-ctrl node for LD11 SoC The LD11 SoC is equipped with SD-ctrl (0x59810000) as well as MIO-ctrl (0x5b3e0000). The SD-ctrl block on this SoC has just one register for controlling RST_n pin of the eMMC device. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
sdctrl@59810000 {
compatible = "socionext,uniphier-ld11-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
sd_rst: reset {
compatible = "socionext,uniphier-ld11-sd-reset";
#reset-cells = <1>;
};
};
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
perictrl@59820000 {
arm64: dts: uniphier: make compatible of syscon nodes SoC-specific These hardware blocks are SoC-specific, so their compatible strings should be SoC-specific as well. This change has no impact on the actual behavior since it is controlled by the generic "simple-mfd", "syscon" compatible strings. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
compatible = "socionext,uniphier-ld11-perictrl",
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
peri_clk: clock {
compatible = "socionext,uniphier-ld11-peri-clock";
#clock-cells = <1>;
};
peri_rst: reset {
compatible = "socionext,uniphier-ld11-peri-reset";
#reset-cells = <1>;
};
};
arm64: dts: uniphier: add eMMC controller node for LD11/LD20 Add Cadence's eMMC controller node for LD11/LD20. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
9 years ago
emmc: sdhc@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
arm64: dts: uniphier: add pinctrl property to eMMC node for LD11/LD20 Now everything is ready to enable this pinctrl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
arm64: dts: uniphier: add eMMC controller node for LD11/LD20 Add Cadence's eMMC controller node for LD11/LD20. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
9 years ago
clocks = <&sys_clk 4>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
arm64: dts: uniphier: add input-delay properties to Cadence eMMC node Since commit a89c472d8b55 ("mmc: sdhci-cadence: Update PHY delay configuration"), PHY parameters must be specified by DT. The hard-coded settings have been converted as follows: - SDHCI_CDNS_PHY_DLY_SD_DEFAULT -> cdns,phy-input-delay-legacy - SDHCI_CDNS_PHY_DLY_EMMC_SDR -> cdns,phy-input-delay-mmc-highspeed - SDHCI_CDNS_PHY_DLY_EMMC_DDR -> cdns,phy-input-delay-mmc-ddr The following have not been moved: - SDHCI_CDNS_PHY_DLY_SD_HS this is unneeded in the eMMC configuration - SDHCI_CDNS_PHY_DLY_EMMC_LEGACY this is never enabled by the driver as it is covered by SDHCI_CDNS_PHY_DLY_SD_DEFAULT Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
arm64: dts: uniphier: add cdns, phy-dll-delay-sdclk(-hsmmc) for eMMC Adjust the PHY parameters for more stable access to the eMMC device. Set the SDCLK output delay value to 21 (including HS200/400 modes). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
cdns,phy-dll-delay-sdclk = <21>;
cdns,phy-dll-delay-sdclk-hsmmc = <21>;
arm64: dts: uniphier: add eMMC controller node for LD11/LD20 Add Cadence's eMMC controller node for LD11/LD20. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
9 years ago
};
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
usb0: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
interrupts = <0 243 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
arm64: dts: uniphier: add STDMAC clock to EHCI nodes Without the STDMAC clock enabled, the USB 2.0 hosts do not work. This clock must be explicitly listed in the "clocks" property because it is independent of the other clocks. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years ago
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
<&mio_clk 12>;
arm64: dts: uniphier: re-order reset deassertion of USB of LD11 Deassert the bit in the System Control block before the MIO block. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
<&mio_rst 12>;
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
};
usb1: usb@5a810100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
interrupts = <0 244 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
arm64: dts: uniphier: add STDMAC clock to EHCI nodes Without the STDMAC clock enabled, the USB 2.0 hosts do not work. This clock must be explicitly listed in the "clocks" property because it is independent of the other clocks. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years ago
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
<&mio_clk 13>;
arm64: dts: uniphier: re-order reset deassertion of USB of LD11 Deassert the bit in the System Control block before the MIO block. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
<&mio_rst 13>;
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
};
usb2: usb@5a820100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
interrupts = <0 245 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
arm64: dts: uniphier: add STDMAC clock to EHCI nodes Without the STDMAC clock enabled, the USB 2.0 hosts do not work. This clock must be explicitly listed in the "clocks" property because it is independent of the other clocks. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years ago
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
<&mio_clk 14>;
arm64: dts: uniphier: re-order reset deassertion of USB of LD11 Deassert the bit in the System Control block before the MIO block. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
<&mio_rst 14>;
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
};
mioctrl@5b3e0000 {
arm64: dts: uniphier: make compatible of syscon nodes SoC-specific These hardware blocks are SoC-specific, so their compatible strings should be SoC-specific as well. This change has no impact on the actual behavior since it is controlled by the generic "simple-mfd", "syscon" compatible strings. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
compatible = "socionext,uniphier-ld11-mioctrl",
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
"simple-mfd", "syscon";
reg = <0x5b3e0000 0x800>;
mio_clk: clock {
compatible = "socionext,uniphier-ld11-mio-clock";
#clock-cells = <1>;
};
mio_rst: reset {
compatible = "socionext,uniphier-ld11-mio-reset";
#reset-cells = <1>;
resets = <&sys_rst 7>;
};
};
soc-glue@5f800000 {
arm64: dts: uniphier: make compatible of syscon nodes SoC-specific These hardware blocks are SoC-specific, so their compatible strings should be SoC-specific as well. This change has no impact on the actual behavior since it is controlled by the generic "simple-mfd", "syscon" compatible strings. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
compatible = "socionext,uniphier-ld11-soc-glue",
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
pinctrl: pinctrl {
compatible = "socionext,uniphier-ld11-pinctrl";
};
};
arm64: dts: uniphier: add AIDET nodes Add UniPhier AIDET (ARM Interrupt Detector) nodes to support active low interrupts. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years ago
aidet: aidet@5fc20000 {
compatible = "socionext,uniphier-ld11-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
gic: interrupt-controller@5fe00000 {
compatible = "arm,gic-v3";
reg = <0x5fe00000 0x10000>, /* GICD */
<0x5fe40000 0x80000>; /* GICR */
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <1 9 4>;
};
sysctrl@61840000 {
compatible = "socionext,uniphier-ld11-sysctrl",
"simple-mfd", "syscon";
arm64: dts: uniphier: increase register region size of sysctrl node The System Control node has 0x10000 byte of registers. The current reg size must be expanded to use the cpufreq driver because the registers controlling CPU frequency are located at offset 0x8000. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
reg = <0x61840000 0x10000>;
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
sys_clk: clock {
compatible = "socionext,uniphier-ld11-clock";
#clock-cells = <1>;
};
sys_rst: reset {
compatible = "socionext,uniphier-ld11-reset";
#reset-cells = <1>;
};
arm64: dts: uniphier: add watchdog node for LD11 and LD20 Add nodes of watchdog timer for UniPhier LD11 and LD20 SoC. The watchdog timer is included in sysctrl. Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
watchdog {
compatible = "socionext,uniphier-wdt";
};
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
};
arm64: dts: uniphier: add Denali NAND controller nodes Add NAND controller node to LD11 and LD20. Neither of them supports the CS1 line, so pinctrl is set up for a single CS line. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years ago
nand: nand@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
};
arm64: dts: uniphier: add LD11 SoC/Board support This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
};
};
arm64: dts: uniphier: use #include instead of /include/ To include dt-bindings headers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years ago
#include "uniphier-pinctrl.dtsi"