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118 lines
5.2 KiB
118 lines
5.2 KiB
20 years ago
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/*
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--------------------------------------------------------------------
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i2c-ite.h: Global defines for the I2C controller on board the
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ITE MIPS processor.
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--------------------------------------------------------------------
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Hai-Pao Fan, MontaVista Software, Inc.
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hpfan@mvista.com or source@mvista.com
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Copyright 2001 MontaVista Software Inc.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef I2C_ITE_H
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#define I2C_ITE_H 1
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#include <asm/it8172/it8172.h>
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/* I2C Registers */
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#define ITE_I2CHCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x30
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#define ITE_I2CHSR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x34
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#define ITE_I2CSAR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x38
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#define ITE_I2CSSAR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x3c
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#define ITE_I2CCKCNT IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x48
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#define ITE_I2CSHDR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x4c
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#define ITE_I2CRSUR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x50
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#define ITE_I2CPSUR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x54
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#define ITE_I2CFDR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x70
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#define ITE_I2CFBCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x74
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#define ITE_I2CFCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x78
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#define ITE_I2CFSR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x7c
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/* Host Control Register ITE_I2CHCR */
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#define ITE_I2CHCR_HCE 0x01 /* Enable I2C Host Controller */
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#define ITE_I2CHCR_IE 0x02 /* Enable the interrupt after completing
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the current transaction */
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#define ITE_I2CHCR_CP_W 0x00 /* bit2-4 000 - Write */
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#define ITE_I2CHCR_CP_R 0x08 /* 010 - Current address read */
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#define ITE_I2CHCR_CP_S 0x10 /* 100 - Sequential read */
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#define ITE_I2CHCR_ST 0x20 /* Initiates the I2C host controller to execute
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the command and send the data programmed in
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all required registers to I2C bus */
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#define ITE_CMD ITE_I2CHCR_HCE | ITE_I2CHCR_IE | ITE_I2CHCR_ST
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#define ITE_WRITE ITE_CMD | ITE_I2CHCR_CP_W
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#define ITE_READ ITE_CMD | ITE_I2CHCR_CP_R
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#define ITE_SREAD ITE_CMD | ITE_I2CHCR_CP_S
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/* Host Status Register ITE_I2CHSR */
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#define ITE_I2CHSR_DB 0x01 /* Device is busy, receives NACK response except
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in the first and last bytes */
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#define ITE_I2CHSR_DNE 0x02 /* Target address on I2C bus does not exist */
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#define ITE_I2CHSR_TDI 0x04 /* R/W Transaction on I2C bus was completed */
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#define ITE_I2CHSR_HB 0x08 /* Host controller is processing transactions */
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#define ITE_I2CHSR_FER 0x10 /* Error occurs in the FIFO */
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/* Slave Address Register ITE_I2CSAR */
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#define ITE_I2CSAR_SA_MASK 0xfe /* Target I2C device address */
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#define ITE_I2CSAR_ASO 0x0100 /* Output 1/0 to I2CAS port when the
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next slave address is addressed */
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/* Slave Sub-address Register ITE_I2CSSAR */
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#define ITE_I2CSSAR_SUBA_MASK 0xff /* Target I2C device sub-address */
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/* Clock Counter Register ITE_I2CCKCNT */
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#define ITE_I2CCKCNT_STOP 0x00 /* stop I2C clock */
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#define ITE_I2CCKCNT_HPCC_MASK 0x7f /* SCL high period counter */
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#define ITE_I2CCKCNT_LPCC_MASK 0x7f00 /* SCL low period counter */
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/* START Hold Time Register ITE_I2CSHDR */
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/* value is counted based on 16 MHz internal clock */
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#define ITE_I2CSHDR_FM 0x0a /* START condition at fast mode */
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#define ITE_I2CSHDR_SM 0x47 /* START contition at standard mode */
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/* (Repeated) START Setup Time Register ITE_I2CRSUR */
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/* value is counted based on 16 MHz internal clock */
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#define ITE_I2CRSUR_FM 0x0a /* repeated START condition at fast mode */
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#define ITE_I2CRSUR_SM 0x50 /* repeated START condition at standard mode */
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/* STOP setup Time Register ITE_I2CPSUR */
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/* FIFO Data Register ITE_I2CFDR */
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#define ITE_I2CFDR_MASK 0xff
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/* FIFO Byte Count Register ITE_I2CFBCR */
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#define ITE_I2CFBCR_MASK 0x3f
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/* FIFO Control Register ITE_I2CFCR */
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#define ITE_I2CFCR_FLUSH 0x01 /* Flush FIFO and reset the FIFO point
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and I2CFSR */
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/* FIFO Status Register ITE_I2CFSR */
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#define ITE_I2CFSR_FO 0x01 /* FIFO is overrun when write */
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#define ITE_I2CFSR_FU 0x02 /* FIFO is underrun when read */
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#define ITE_I2CFSR_FF 0x04 /* FIFO is full when write */
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#define ITE_I2CFSR_FE 0x08 /* FIFO is empty when read */
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#endif /* I2C_ITE_H */
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