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90 lines
2.4 KiB
90 lines
2.4 KiB
20 years ago
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/*
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* Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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*/
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#include <linux/config.h>
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#ifndef __OVERDRIVE_H__
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#define __OVERDRIVE_H__
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#define OVERDRIVE_INT_CT 0xa3a00000
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#define OVERDRIVE_INT_DT 0xa3b00000
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#define OVERDRIVE_CTRL 0xa3000000
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/* Shoving all these bits into the same register is not a good idea.
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* As soon as I get a spare moment, I'll change the FPGA and put each
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* bit in a separate register
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*/
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#define VALID_CTRL_BITS 0x1f
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#define ENABLE_RS232_MASK 0x1e
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#define DISABLE_RS232_BIT 0x01
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#define ENABLE_NMI_MASK 0x1d
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#define DISABLE_NMI_BIT 0x02
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#define RESET_PCI_MASK 0x1b
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#define ENABLE_PCI_BIT 0x04
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#define ENABLE_LED_MASK 0x17
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#define DISABLE_LED_BIT 0x08
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#define RESET_FPGA_MASK 0x0f
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#define ENABLE_FPGA_BIT 0x10
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#define FPGA_DCLK_ADDRESS 0xA3C00000
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#define FPGA_DATA 0x01 /* W */
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#define FPGA_CONFDONE 0x02 /* R */
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#define FPGA_NOT_STATUS 0x04 /* R */
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#define FPGA_INITDONE 0x08 /* R */
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#define FPGA_TIMEOUT 100000
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/* Interrupts for the overdrive. Note that these numbers have
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* nothing to do with the actual IRQ numbers they appear on,
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* this is all programmable. This is simply the position in the
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* INT_CT register.
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*/
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#define OVERDRIVE_PCI_INTA 0
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#define OVERDRIVE_PCI_INTB 1
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#define OVERDRIVE_PCI_INTC 2
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#define OVERDRIVE_PCI_INTD 3
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#define OVERDRIVE_GALILEO_INT 4
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#define OVERDRIVE_GALILEO_LOCAL_INT 5
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#define OVERDRIVE_AUDIO_INT 6
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#define OVERDRIVE_KEYBOARD_INT 7
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/* Which Linux IRQ should we assign to each interrupt source? */
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#define OVERDRIVE_PCI_IRQ1 2
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#ifdef CONFIG_HACKED_NE2K
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#define OVERDRIVE_PCI_IRQ2 7
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#else
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#define OVERDRIVE_PCI_IRQ2 2
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#undef OVERDRIVE_PCI_INTB
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#define OVERDRIVE_PCI_INTB OVERDRIVE_PCI_INTA
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#endif
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/* Put the ESS solo audio chip on IRQ 4 */
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#define OVERDRIVE_ESS_IRQ 4
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/* Where the memory behind the PCI bus appears */
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#define PCI_DRAM_BASE 0xb7000000
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#define PCI_DRAM_SIZE (16*1024*1024)
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#define PCI_DRAM_FINISH (PCI_DRAM_BASE+PCI_DRAM_SIZE-1)
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/* Where the IO region appears in the memory */
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#define PCI_GTIO_BASE 0xb8000000
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#endif
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